component
SN74LVC573APW
Public Unreviewedby Ray
Texas Instruments Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownSN74LVC573APW
Texas Instruments · Latches · TSSOP-20
SN74LVC573APW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Output-enable, active low. When OE is low the 3-state Q outputs are driven; when OE is high all Q outputs are placed in the high-impedance state. Latching action on D/LE is unaffected by OE. |
| 2 | 1D | input | Data input 1 to the octal transparent latch. Sampled by 1Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 3 | 2D | input | Data input 2 to the octal transparent latch. Sampled by 2Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 4 | 3D | input | Data input 3 to the octal transparent latch. Sampled by 3Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 5 | 4D | input | Data input 4 to the octal transparent latch. Sampled by 4Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 6 | 5D | input | Data input 5 to the octal transparent latch. Sampled by 5Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 7 | 6D | input | Data input 6 to the octal transparent latch. Sampled by 6Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 8 | 7D | input | Data input 7 to the octal transparent latch. Sampled by 7Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 9 | 8D | input | Data input 8 to the octal transparent latch. Sampled by 8Q while LE is high and held on the falling edge of LE. 5.5 V tolerant. |
| 10 | GND | power_in | Ground reference (0 V) for the device. Connect to system ground with a low-impedance return. |
| 11 | LE | input | Latch-enable, active high. While LE is high the latch is transparent and each Q follows its D input; on the falling edge of LE the eight D values are captured and held on Q. Minimum LE-high pulse width is 3.3 ns at VCC=3.3 V. |
| 12 | 8Q | tri_state | 3-state latched output 8. Drives the value captured from 8D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 13 | 7Q | tri_state | 3-state latched output 7. Drives the value captured from 7D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 14 | 6Q | tri_state | 3-state latched output 6. Drives the value captured from 6D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 15 | 5Q | tri_state | 3-state latched output 5. Drives the value captured from 5D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 16 | 4Q | tri_state | 3-state latched output 4. Drives the value captured from 4D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 17 | 3Q | tri_state | 3-state latched output 3. Drives the value captured from 3D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 18 | 2Q | tri_state | 3-state latched output 2. Drives the value captured from 2D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 19 | 1Q | tri_state | 3-state latched output 1. Drives the value captured from 1D; high-impedance when OE is high. Rated up to IOL=24 mA / IOH=-24 mA at VCC=3 V. |
| 20 | VCC | power_in | Positive supply, 1.65 V to 3.6 V operating (data retention down to 1.5 V). Decouple locally with a 0.1 µF ceramic capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Ordering variants
Same part, different packaging or reel option.
SN74LVC573APWSN74LVC573APWRSN74LVC573APWTSN74LVC573APWDBSN74LVC573APWDBRSN74LVC573APWDGVSN74LVC573APWDGVRSN74LVC573APWDWSN74LVC573APWDWRSN74LVC573APWNSN74LVC573APWNSSN74LVC573APWNSRSN74LVC573APWRGYSN74LVC573APWRGYRSN74LVC573APWGQNSN74LVC573APWZQN
CAD (KiCad official)
- Symbol:
SN74LVC573APW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
e5b427be8a90b0ba, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).