component

SN74LVC540APWR

Public Unreviewed

by Ray

Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentlogicsn74lvc540apwr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

SN74LVC540APWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74LVC540APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Output enable 1, active low. Must be low (along with OE2) to enable all eight buffer outputs; otherwise the Y outputs go to high impedance. Tie to VCC through a pull-up (Ioff supports live insertion) during power-up/down to hold Hi-Z.
2 A1 input Input for channel 1. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y1. Input voltage range 0 to 5.5V (5V-tolerant with 3.3V VCC).
3 A2 input Input for channel 2. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y2. Input voltage range 0 to 5.5V.
4 A3 input Input for channel 3. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y3. Input voltage range 0 to 5.5V.
5 A4 input Input for channel 4. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y4. Input voltage range 0 to 5.5V.
6 A5 input Input for channel 5. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y5. Input voltage range 0 to 5.5V.
7 A6 input Input for channel 6. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y6. Input voltage range 0 to 5.5V.
8 A7 input Input for channel 7. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y7. Input voltage range 0 to 5.5V.
9 A8 input Input for channel 8. Standard CMOS input, high impedance; drives inverting 3-state buffer output Y8. Input voltage range 0 to 5.5V.
10 GND power_in Ground reference (0V). Provides return path for VCC and reference for logic thresholds.
11 Y8 tri_state Inverting 3-state buffer output for channel 8 (Y8 = /A8 when OE1=OE2=L; Hi-Z otherwise). IOH up to -24mA and IOL up to 24mA at VCC=3V.
12 Y7 tri_state Inverting 3-state buffer output for channel 7 (Y7 = /A7 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
13 Y6 tri_state Inverting 3-state buffer output for channel 6 (Y6 = /A6 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
14 Y5 tri_state Inverting 3-state buffer output for channel 5 (Y5 = /A5 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
15 Y4 tri_state Inverting 3-state buffer output for channel 4 (Y4 = /A4 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
16 Y3 tri_state Inverting 3-state buffer output for channel 3 (Y3 = /A3 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
17 Y2 tri_state Inverting 3-state buffer output for channel 2 (Y2 = /A2 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
18 Y1 tri_state Inverting 3-state buffer output for channel 1 (Y1 = /A1 when enabled; Hi-Z otherwise). Balanced CMOS drive up to ±24mA at VCC=3V.
19 OE2 input Output enable 2, active low. Must be low (along with OE1) to enable all eight buffer outputs; otherwise the Y outputs go to high impedance. Tie to VCC through a pull-up during power-up/down to hold Hi-Z.
20 VCC power_in Positive supply, 1.65V to 3.6V operating (1.5V data retention only). Bypass to GND with a local decoupling capacitor near the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74LVC540APWR
  • SN74LVC540APWRDW
  • SN74LVC540APWRDWR
  • SN74LVC540APWRDB
  • SN74LVC540APWRDBR
  • SN74LVC540APWRNS
  • SN74LVC540APWRNSR
  • SN74LVC540APWRDGS
  • SN74LVC540APWRDGSR
  • SN74LVC540APWRDGV
  • SN74LVC540APWRDGVR
  • SN74LVC540APWRRKS
  • SN74LVC540APWRRKSR

CAD (KiCad official)

  • Symbol: SN74LVC540APWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 a821ecd693b551c0, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF