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SN74LVC1G80DCKR

Texas Instruments · Flip Flops · SC-70-5

SN74LVC1G80DCKR from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input Data input. Sampled on the positive-going edge of CLK when setup/hold timing is met. Standard CMOS input, high impedance, accepts 0V to 5.5V regardless of VCC.
2 CLK input Positive-edge-triggered clock input. Data at D is latched to Q̄ on the rising edge; fmax = 160MHz. Standard CMOS input, 5.5V-tolerant.
3 GND power_in Ground reference (0V). Return for VCC supply current.
4 Q output Inverted flip-flop output (Q̄). Balanced high-drive CMOS push-pull output; ±24mA at 3.3V. Enters high-Z when VCC = 0V (Ioff partial-power-down).
5 VCC power_in Positive supply, 1.65V to 5.5V operating (1.5V data retention). Bypass with 0.1µF (and optionally 1µF) close to the pin. Absolute max 6.5V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Logic
Pins 5

Ordering variants

  • SN74LVC1G80DCKR
  • SN74LVC1G80DCKRDCKT
  • SN74LVC1G80DCKRG4
  • SN74LVC1G80DCKRDBVR
  • SN74LVC1G80DCKRDBVT
  • SN74LVC1G80DCKRDBVRE4
  • SN74LVC1G80DCKRDBVRG4
  • SN74LVC1G80DCKRYZPR

CAD (KiCad official)

  • Symbol: SN74LVC1G80DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 73b5b60e38105033, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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