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Contents

README

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SN74LV594ADBR

Texas Instruments · Shifting Register · SSOP-16-208mil

SN74LV594ADBR from Texas Instruments, in a SSOP-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB output Parallel output B from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
2 QC output Parallel output C from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
3 QD output Parallel output D from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
4 QE output Parallel output E from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
5 QF output Parallel output F from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
6 QG output Parallel output G from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
7 QH output Parallel output H from the storage register (LSB/MSB depending on shift direction). Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
8 GND power_in Ground reference (0 V). Connect to the system ground plane.
9 QH' output Serial cascade output tapped from the shift register (Q_H inverted / serial-out). Route to the SER input of the next SN74LV594A when cascading multiple devices for wider shift registers.
10 SRCLR input Active-low asynchronous serial-register clear. Driving low resets the internal 8-bit shift register without affecting the storage register.
11 SRCLK input Serial-register clock. Rising edge shifts data on SER into the 8-bit shift register.
12 RCLK input Storage-register (latch) clock. Rising edge transfers the contents of the shift register into the parallel-output storage register.
13 RCLR input Active-low asynchronous storage-register clear. Driving low resets the parallel-output storage register (Q_A..Q_H → 0) without affecting the shift register.
14 SER input Serial data input. Sampled on the rising edge of SRCLK and shifted into the first stage of the 8-bit shift register.
15 QA output Parallel output A from the storage register. Push-pull CMOS output; drive capability up to ±12 mA at VCC = 4.5 V.
16 VCC power_in Positive supply voltage, 2 V to 5.5 V recommended (7 V absolute max). Bypass locally with 0.1 µF ceramic to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-16-208mil
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74LV594ADBR
  • SN74LV594ADBRDR
  • SN74LV594ADBRD
  • SN74LV594ADBRPWR
  • SN74LV594ADBRPW
  • SN74LV594ADBRBQB

CAD (KiCad official)

  • Symbol: SN74LV594ADBR
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16-208mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 457d89138c4eb261, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF