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SN74LV374APW

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by Ray

Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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SN74LV374APW

Texas Instruments · Flip Flops · TSSOP-20

SN74LV374APW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low 3-state output-enable input. When OE is low, all eight Q outputs are enabled; when OE is high, all eight Q outputs are placed in the high-impedance (Hi-Z) state.
2 1Q tri_state Register output 1. 3-state CMOS output following 1D on the rising edge of CLK; drives up to IOH/IOL = ±16 mA at VCC = 4.5 V.
3 1D input Data input 1. CMOS logic input clocked into flip-flop 1 on the rising edge of CLK.
4 2D input Data input 2. CMOS logic input clocked into flip-flop 2 on the rising edge of CLK.
5 2Q tri_state Register output 2. 3-state CMOS output following 2D on the rising edge of CLK.
6 3Q tri_state Register output 3. 3-state CMOS output following 3D on the rising edge of CLK.
7 3D input Data input 3. CMOS logic input clocked into flip-flop 3 on the rising edge of CLK.
8 4D input Data input 4. CMOS logic input clocked into flip-flop 4 on the rising edge of CLK.
9 4Q tri_state Register output 4. 3-state CMOS output following 4D on the rising edge of CLK.
10 GND power_in Ground reference (0 V). Common return for all supply and signal currents.
11 CLK input Clock input. All eight D inputs are latched into their respective flip-flops on the rising (positive) edge of CLK.
12 5Q tri_state Register output 5. 3-state CMOS output following 5D on the rising edge of CLK.
13 5D input Data input 5. CMOS logic input clocked into flip-flop 5 on the rising edge of CLK.
14 6D input Data input 6. CMOS logic input clocked into flip-flop 6 on the rising edge of CLK.
15 6Q tri_state Register output 6. 3-state CMOS output following 6D on the rising edge of CLK.
16 7Q tri_state Register output 7. 3-state CMOS output following 7D on the rising edge of CLK.
17 7D input Data input 7. CMOS logic input clocked into flip-flop 7 on the rising edge of CLK.
18 8D input Data input 8. CMOS logic input clocked into flip-flop 8 on the rising edge of CLK.
19 8Q tri_state Register output 8. 3-state CMOS output following 8D on the rising edge of CLK.
20 VCC power_in Positive supply input, 2 V to 5.5 V. Bypass to GND with a 0.1 µF ceramic capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74LV374APW
  • SN74LV374APWR
  • SN74LV374APWT
  • SN74LV374APWDB
  • SN74LV374APWDBR
  • SN74LV374APWDW
  • SN74LV374APWDWR
  • SN74LV374APWNS
  • SN74LV374APWNSR

CAD (KiCad official)

  • Symbol: SN74LV374APW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 7a440a5280268468, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF