SN74LV245ANSR from Texas Instruments, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DIR	input	Direction control input. When HIGH, data flows from A-port to B-port (A -> B). When LOW, data flows from B-port to A-port (B -> A). CMOS-level input.
2	A1	bidirectional	A-port channel 1 data I/O. Direction set by DIR; placed in high-impedance state when OE is HIGH. Supports mixed-mode voltage operation and partial-power-down (Ioff).
3	A2	bidirectional	A-port channel 2 data I/O. Direction set by DIR; high-Z when OE is HIGH.
4	A3	bidirectional	A-port channel 3 data I/O. Direction set by DIR; high-Z when OE is HIGH.
5	A4	bidirectional	A-port channel 4 data I/O. Direction set by DIR; high-Z when OE is HIGH.
6	A5	bidirectional	A-port channel 5 data I/O. Direction set by DIR; high-Z when OE is HIGH.
7	A6	bidirectional	A-port channel 6 data I/O. Direction set by DIR; high-Z when OE is HIGH.
8	A7	bidirectional	A-port channel 7 data I/O. Direction set by DIR; high-Z when OE is HIGH.
9	A8	bidirectional	A-port channel 8 data I/O. Direction set by DIR; high-Z when OE is HIGH.
10	GND	power_in	Ground reference (0 V). Tie to the system ground plane; continuous current through VCC or GND is limited to +/-70 mA.
11	B8	bidirectional	B-port channel 8 data I/O. Direction set by DIR; high-Z when OE is HIGH.
12	B7	bidirectional	B-port channel 7 data I/O. Direction set by DIR; high-Z when OE is HIGH.
13	B6	bidirectional	B-port channel 6 data I/O. Direction set by DIR; high-Z when OE is HIGH.
14	B5	bidirectional	B-port channel 5 data I/O. Direction set by DIR; high-Z when OE is HIGH.
15	B4	bidirectional	B-port channel 4 data I/O. Direction set by DIR; high-Z when OE is HIGH.
16	B3	bidirectional	B-port channel 3 data I/O. Direction set by DIR; high-Z when OE is HIGH.
17	B2	bidirectional	B-port channel 2 data I/O. Direction set by DIR; high-Z when OE is HIGH.
18	B1	bidirectional	B-port channel 1 data I/O. Direction set by DIR; high-Z when OE is HIGH.
19	~OE	input	Output enable, active LOW. When LOW, the A and B ports are enabled and driven per DIR. When HIGH, both ports are placed in the high-impedance (3-state) state, isolating the transceiver from the bus.
20	VCC	power_in	Positive supply. Recommended operating range 2 V to 5.5 V. Bypass with a local decoupling capacitor at the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-20-208mil
Category	Logic
Pins	20

Ordering variants

Same part, different packaging or reel option.

SN74LV245ANSR
SN74LV245ANSRDB
SN74LV245ANSRDBR
SN74LV245ANSRDGV
SN74LV245ANSRDGVR
SN74LV245ANSRDW
SN74LV245ANSRDWR
SN74LV245ANSRPW
SN74LV245ANSRPWR
SN74LV245ANSRRGY
SN74LV245ANSRRGYR
SN74LV245ANSRW
SN74LV245ANSRJ
SN74LV245ANSRFK
SN74LV245ANSRGQN

CAD (KiCad official)

Symbol: SN74LV245ANSR
Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
3D model: SOIC-20-208mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 15ef3ebb3b068efe, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF