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sn74lv164apwr
Public Unreviewedby Ray
Texas Instruments Shifting Register, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSN74LV164APWR
Texas Instruments · Shifting Register · TSSOP-14
SN74LV164APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Serial data input A. ANDed internally with serial input B; the AND result is shifted into QA on the rising edge of CLK. Must be tied to VCC or GND if unused. |
| 2 | B | input | Serial data input B. ANDed internally with serial input A; tie to VCC (or to A) when only a single serial data input is needed. |
| 3 | QA | output | Shift-register output bit A (first stage). Push-pull CMOS output; drives ±12 mA at VCC = 4.5 V to 5.5 V, ±6 mA at 3 V to 3.6 V. |
| 4 | QB | output | Shift-register output bit B (second stage). Push-pull CMOS output rated ±12 mA at 5 V. |
| 5 | QC | output | Shift-register output bit C (third stage). Push-pull CMOS output rated ±12 mA at 5 V. |
| 6 | QD | output | Shift-register output bit D (fourth stage). Push-pull CMOS output rated ±12 mA at 5 V. |
| 7 | GND | power_in | Ground reference (0 V) for the device. Must be tied to the system ground; continuous current through GND is limited to ±50 mA. |
| 8 | CLK | input | Shift (storage) clock input. Data at (A AND B) is sampled and advanced through the register on the rising edge of CLK; minimum high/low pulse width 5 ns at VCC = 3.3 V. |
| 9 | CLR | input | Asynchronous clear input, active low. Driving CLR low forces all eight Q outputs to logic 0 independent of CLK; minimum low pulse width 5 ns at VCC = 3.3 V. |
| 10 | QE | output | Shift-register output bit E (fifth stage). Push-pull CMOS output rated ±12 mA at 5 V. |
| 11 | QF | output | Shift-register output bit F (sixth stage). Push-pull CMOS output rated ±12 mA at 5 V. |
| 12 | QG | output | Shift-register output bit G (seventh stage). Push-pull CMOS output rated ±12 mA at 5 V. |
| 13 | QH | output | Shift-register output bit H (eighth/last stage). Push-pull CMOS output rated ±12 mA at 5 V; used as the serial-out for cascading multiple 'LV164A devices. |
| 14 | VCC | power_in | Positive supply pin, 2 V to 5.5 V (absolute max 7 V). Bypass locally to GND with a 0.1 µF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
SN74LV164APWRSN74LV164APWRDSN74LV164APWRDRSN74LV164APWRDBSN74LV164APWRDBRSN74LV164APWRDGVSN74LV164APWRDGVRSN74LV164APWRNSSN74LV164APWRNSRSN74LV164APWRRGYSN74LV164APWRRGYRSN74LV164APWRBQASN74LV164APWRBQAR
CAD (KiCad official)
- Symbol:
SN74LV164APWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
6789cef5ba0c0c25, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).