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sn74lv123adr

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by Ray

Texas Instruments Monostable Multivibrators, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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SN74LV123ADR

Texas Instruments · Monostable Multivibrators · SOIC-16

SN74LV123ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 falling-edge trigger input (active when 1B = H). Hold low when other input methods are used. Schmitt-trigger input; VIH/VIL thresholds scale with VCC (typ 0.7VCC / 0.3VCC).
2 1B input Channel 1 rising-edge trigger input (active when 1A = L). Hold high when other input methods are used. Schmitt-trigger input.
3 1CLR input Channel 1 clear / active-high edge trigger (rising edge triggers when 1A = H and 1B = L). Driving low during the output pulse terminates it early. Schmitt-trigger input.
4 1Q output Channel 1 inverted output (1Q-bar). Push-pull CMOS output; IOH/IOL up to +/-12 mA at VCC = 4.5-5.5 V.
5 2Q output Channel 2 non-inverted output. Push-pull CMOS output; IOH/IOL up to +/-12 mA at VCC = 4.5-5.5 V.
6 2Cext passive Channel 2 external timing capacitor negative connection. Connect the timing capacitor Cext between 2Cext and 2Rext/Cext (positive terminal on 2Rext/Cext).
7 2Rext/Cext passive Channel 2 external timing R/C junction. Connect Cext to 2Cext (pin 6) and Rext from this node to VCC. Rext = 1 kΩ min for VCC >= 3 V (5 kΩ min at 2 V); Cext has no restriction.
8 GND power_in Device ground reference (0 V). Continuous current through VCC or GND is limited to +/-50 mA (absolute maximum).
9 2A input Channel 2 falling-edge trigger input (active when 2B = H). Hold low when other input methods are used. Schmitt-trigger input.
10 2B input Channel 2 rising-edge trigger input (active when 2A = L). Hold high when other input methods are used. Schmitt-trigger input.
11 2CLR input Channel 2 clear / active-high edge trigger (rising edge triggers when 2A = H and 2B = L). Driving low during the output pulse terminates it early. Schmitt-trigger input.
12 2Q output Channel 2 inverted output (2Q-bar). Push-pull CMOS output; IOH/IOL up to +/-12 mA at VCC = 4.5-5.5 V.
13 1Q output Channel 1 non-inverted output. Push-pull CMOS output; IOH/IOL up to +/-12 mA at VCC = 4.5-5.5 V.
14 1Cext passive Channel 1 external timing capacitor negative connection. Connect Cext between 1Cext and 1Rext/Cext (positive terminal on 1Rext/Cext).
15 1Rext/Cext passive Channel 1 external timing R/C junction. Connect Cext to 1Cext (pin 14) and Rext from this node to VCC. Rext = 1 kΩ min for VCC >= 3 V (5 kΩ min at 2 V).
16 VCC power_in Positive supply voltage, 2 V to 5.5 V (absolute max 7 V). Also the pull-up rail for the external timing resistor Rext. Power-up ramp rate must be >= 1 ms/V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

  • SN74LV123ADRD
  • SN74LV123ADR
  • SN74LV123ADRDB
  • SN74LV123ADRDBR
  • SN74LV123ADRNS
  • SN74LV123ADRNSR
  • SN74LV123ADRPW
  • SN74LV123ADRPWR
  • SN74LV123ADRDGV
  • SN74LV123ADRDGVR
  • SN74LV123ADRRGY
  • SN74LV123ADRRGYR

CAD (KiCad official)

  • Symbol: SN74LV123ADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 177536726ba54dee, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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