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SN74LS123DR

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by Ray

Texas Instruments Monostable Multivibrators, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN74LS123DR

Texas Instruments · Monostable Multivibrators · SOIC-16

SN74LS123DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 active-low gated trigger input A. A high-to-low transition on 1A (with 1B=H and 1CLR=H) triggers the one-shot output pulse on 1Q.
2 1B input Channel 1 active-high gated trigger input B (Schmitt-trigger on LS variants). A low-to-high transition on 1B (with 1A=L and 1CLR=H) triggers the one-shot.
3 1CLR input Channel 1 active-low overriding clear input. A low level on 1CLR terminates the output pulse and inhibits triggering; a rising edge with A=L, B=H also triggers the one-shot.
4 1Q output Channel 1 non-inverted monostable output. Idles low, goes high for the programmed pulse duration tw when triggered.
5 2Q output Channel 2 inverted monostable output (2Q-bar). Idles high, goes low for the programmed pulse duration when channel 2 is triggered.
6 2Cext passive Channel 2 external timing-capacitor terminal. Connect Cext between 2Cext and 2Rext/Cext; the pulse width is tW ≈ 0.33 · RT · Cext for Cext ≥ 1 µF.
7 2Rext/Cext passive Channel 2 combined timing resistor / capacitor node. Connect external timing resistor Rext (5 kΩ to 260 kΩ) from this pin to VCC and Cext from this pin to 2Cext.
8 GND power_in Device ground reference (0 V). All voltages are referenced to this pin.
9 2A input Channel 2 active-low gated trigger input A. A high-to-low transition on 2A (with 2B=H and 2CLR=H) triggers the channel-2 one-shot.
10 2B input Channel 2 active-high gated trigger input B (Schmitt-trigger on LS variants). A low-to-high transition on 2B (with 2A=L and 2CLR=H) triggers the channel-2 one-shot.
11 2CLR input Channel 2 active-low overriding clear input. A low level terminates the channel-2 output pulse and inhibits triggering.
12 2Q output Channel 2 non-inverted monostable output. Idles low, goes high for the programmed pulse duration tw when channel 2 is triggered.
13 1Q output Channel 1 inverted monostable output (1Q-bar). Idles high, goes low for the programmed pulse duration when channel 1 is triggered.
14 1Cext passive Channel 1 external timing-capacitor terminal. Connect Cext between 1Cext and 1Rext/Cext; note that this pin is internally tied to the Cext ground return.
15 1Rext/Cext passive Channel 1 combined timing resistor / capacitor node. Connect external timing resistor Rext (5 kΩ to 260 kΩ for SN74LS) from this pin to VCC and Cext from this pin to 1Cext.
16 VCC power_in Positive supply input, 4.75 V to 5.25 V (5 V nominal). Also supplies the timing resistor Rext current.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74LS123DR
  • SN74LS123DRD
  • SN74LS123DRN
  • SN74LS123DRJ
  • SN74LS123DRW
  • SN74LS123DRFK

CAD (KiCad official)

  • Symbol: SN74LS123DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 f42431e5273d6423, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF