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SN74HC595PWR
Public Unreviewedby Ray
Texas Instruments Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC595PWR
Texas Instruments · Shift Registers · TSSOP-16
SN74HC595PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Parallel output B from the 8-bit storage register. 3-state output; disabled to high-impedance when OE is high. Can source/sink up to ±6 mA at 5 V. |
| 2 | QC | tri_state | Parallel output C from the 8-bit storage register. 3-state output; high-impedance when OE is high. |
| 3 | QD | tri_state | Parallel output D from the 8-bit storage register. 3-state output; high-impedance when OE is high. |
| 4 | QE | tri_state | Parallel output E from the 8-bit storage register. 3-state output; high-impedance when OE is high. |
| 5 | QF | tri_state | Parallel output F from the 8-bit storage register. 3-state output; high-impedance when OE is high. |
| 6 | QG | tri_state | Parallel output G from the 8-bit storage register. 3-state output; high-impedance when OE is high. |
| 7 | QH | tri_state | Parallel output H (MSB) from the 8-bit storage register. 3-state output; high-impedance when OE is high. |
| 8 | GND | power_in | Ground reference pin. Must be tied to 0 V (system ground). |
| 9 | QH' | output | Serial output from the shift register (not gated by OE). Provides the shift-register data to allow cascading multiple SN74HC595 devices; connect to the SER input of the next stage. |
| 10 | SRCLR | input | Active-low shift-register clear (SRCLR). Driving low asynchronously clears the 8-bit shift register; does not affect the storage register. Tie high (VCC) for normal operation. |
| 11 | SRCLK | input | Shift-register clock input. Data on SER is shifted into the 8-bit shift register on the rising edge of SRCLK. Max clock frequency ~25 MHz at VCC=6 V. |
| 12 | RCLK | input | Storage-register (latch) clock input. Rising edge transfers the contents of the shift register into the 8-bit storage register, updating the QA-QH outputs. |
| 13 | OE | input | Active-low output enable. When low, the QA-QH 3-state outputs are enabled; when high, they are in the high-impedance state. Does not affect the internal registers. |
| 14 | SER | input | Serial data input to the shift register. The bit present on SER is loaded into the LSB of the shift register on the rising edge of SRCLK. |
| 15 | QA | tri_state | Parallel output A (LSB) from the 8-bit storage register. 3-state output; high-impedance when OE is high. Can drive ±6 mA at 5 V. |
| 16 | VCC | power_in | Positive supply. Recommended operating range 2 V to 6 V (absolute max 7 V). Bypass locally with a 0.1 µF capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
SN74HC595PWRSN74HC595PWRDSN74HC595PWRDRSN74HC595PWRDWSN74HC595PWRDWRSN74HC595PWRDBSN74HC595PWRDBRSN74HC595PWRNSN74HC595PWRNSSN74HC595PWRNSRSN74HC595PWRJSN74HC595PWRFK
CAD (KiCad official)
- Symbol:
SN74HC595PWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
215816945704e561, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).