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sn74hc374pwr

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by Ray

Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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SN74HC374PWR

Texas Instruments · Flip Flops · TSSOP-20

SN74HC374PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output-enable, active LOW. When HIGH, all Q outputs are placed in the high-impedance (Hi-Z) state; when LOW, outputs are enabled and driven by the internal latches.
2 1Q tri_state 3-state data output for channel 1. Reflects the value latched from 1D on the rising edge of CLK when OE is LOW.
3 1D input Data input for channel 1. Sampled on the rising edge of CLK and stored in the channel 1 flip-flop.
4 2D input Data input for channel 2. Sampled on the rising edge of CLK and stored in the channel 2 flip-flop.
5 2Q tri_state 3-state data output for channel 2. Reflects the value latched from 2D on the rising edge of CLK when OE is LOW.
6 3Q tri_state 3-state data output for channel 3. Reflects the value latched from 3D on the rising edge of CLK when OE is LOW.
7 3D input Data input for channel 3. Sampled on the rising edge of CLK and stored in the channel 3 flip-flop.
8 4D input Data input for channel 4. Sampled on the rising edge of CLK and stored in the channel 4 flip-flop.
9 4Q tri_state 3-state data output for channel 4. Reflects the value latched from 4D on the rising edge of CLK when OE is LOW.
10 GND power_in Ground reference (0 V). Must be tied to the system ground.
11 CLK input Clock input. On its LOW-to-HIGH (rising) edge, the data present at all eight D inputs is transferred to the corresponding Q outputs (when OE is LOW).
12 5Q tri_state 3-state data output for channel 5. Reflects the value latched from 5D on the rising edge of CLK when OE is LOW.
13 5D input Data input for channel 5. Sampled on the rising edge of CLK and stored in the channel 5 flip-flop.
14 6D input Data input for channel 6. Sampled on the rising edge of CLK and stored in the channel 6 flip-flop.
15 6Q tri_state 3-state data output for channel 6. Reflects the value latched from 6D on the rising edge of CLK when OE is LOW.
16 7Q tri_state 3-state data output for channel 7. Reflects the value latched from 7D on the rising edge of CLK when OE is LOW.
17 7D input Data input for channel 7. Sampled on the rising edge of CLK and stored in the channel 7 flip-flop.
18 8D input Data input for channel 8. Sampled on the rising edge of CLK and stored in the channel 8 flip-flop.
19 8Q tri_state 3-state data output for channel 8. Reflects the value latched from 8D on the rising edge of CLK when OE is LOW.
20 VCC power_in Positive supply voltage. Operating range 2 V to 6 V. Decouple to GND with a 0.1 µF ceramic capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74HC374PWR
  • SN74HC374PWRDWR
  • SN74HC374PWRDW
  • SN74HC374PWRNSR
  • SN74HC374PWRNS
  • SN74HC374PWRN

CAD (KiCad official)

  • Symbol: SN74HC374PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 623d16419cf34e46, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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