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SN74HC273NSR

lingxingic SN74HC273NSR LX · Flip Flops · SOIC-20-208mil

SN74HC273NSR from lingxingic SN74HC273NSR LX, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master reset input, active low. Driving MR low asynchronously forces all eight Qn outputs to logic low, independent of CP and Dn. CMOS-level (HC) or TTL-level (HCT) input.
2 Q0 output Flip-flop 0 data output. Registered version of D0, updated on the rising edge of CP; forced low when MR is asserted low.
3 D0 input Flip-flop 0 data input. Sampled on the rising edge of CP and transferred to Q0, provided setup/hold times are met.
4 D1 input Flip-flop 1 data input. Sampled on the rising edge of CP and transferred to Q1.
5 Q1 output Flip-flop 1 data output. Registered version of D1; forced low when MR is asserted low.
6 Q2 output Flip-flop 2 data output. Registered version of D2; forced low when MR is asserted low.
7 D2 input Flip-flop 2 data input. Sampled on the rising edge of CP and transferred to Q2.
8 D3 input Flip-flop 3 data input. Sampled on the rising edge of CP and transferred to Q3.
9 Q3 output Flip-flop 3 data output. Registered version of D3; forced low when MR is asserted low.
10 GND power_in Ground reference, 0 V. Common return for VCC and all logic signals.
11 CP input Clock input, common to all eight flip-flops. Rising edge samples the Dn inputs into Qn (subject to setup/hold). Recommended input rise/fall rate ≤139 ns/V at VCC=4.5 V.
12 Q4 output Flip-flop 4 data output. Registered version of D4; forced low when MR is asserted low.
13 D4 input Flip-flop 4 data input. Sampled on the rising edge of CP and transferred to Q4.
14 D5 input Flip-flop 5 data input. Sampled on the rising edge of CP and transferred to Q5.
15 Q5 output Flip-flop 5 data output. Registered version of D5; forced low when MR is asserted low.
16 Q6 output Flip-flop 6 data output. Registered version of D6; forced low when MR is asserted low.
17 D6 input Flip-flop 6 data input. Sampled on the rising edge of CP and transferred to Q6.
18 D7 input Flip-flop 7 data input. Sampled on the rising edge of CP and transferred to Q7.
19 Q7 output Flip-flop 7 data output. Registered version of D7; forced low when MR is asserted low.
20 VCC power_in Positive supply voltage. Recommended 2.0-6.0 V for SN74HC273 and 4.5-5.5 V for SN74HCT273. Absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer lingxingic SN74HC273NSR LX
Package SOIC-20-208mil
Category Logic
Pins 20

Ordering variants

  • SN74HC273NSR
  • SN74HC273NSRN
  • SN74HC273NSRD
  • SN74HC273NSRPW

CAD (KiCad official)

  • Symbol: SN74HC273NSR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-208mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic SN74HC273NSR LX datasheet (None pp, sha256 a26108f4267548db, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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