component
SN74HC259DR
Public Unreviewedby Ray
Texas Instruments Latches, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC259DR
Texas Instruments · Latches · SOIC-16
SN74HC259DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S0 | input | Address select input bit 0 (LSB). Selects which of eight latches receives the D input or is asserted as the active output in decoder mode. CMOS logic input, VIH >= 0.7*VCC. |
| 2 | S1 | input | Address select input bit 1. Combined with S0 and S2 forms a 3-bit address selecting one of eight internal latches / decoder outputs. |
| 3 | S2 | input | Address select input bit 2 (MSB). Combined with S0/S1 forms the 3-bit address that selects the active latch or demux output. |
| 4 | Q0 | output | Latched active-high output 0. Drives approximately +/-4 mA at VCC = 5 V (up to 10 LSTTL loads). In addressable-latch mode holds the last data written to address 000; in demux mode follows D when addressed and is low otherwise. |
| 5 | Q1 | output | Latched active-high output 1. Same electrical characteristics as Q0; selected by address 001. |
| 6 | Q2 | output | Latched active-high output 2. Selected by address 010. |
| 7 | Q3 | output | Latched active-high output 3. Selected by address 011. |
| 8 | GND | power_in | Device ground reference (0 V). Must be connected to system ground and decoupled together with VCC. |
| 9 | Q4 | output | Latched active-high output 4. Selected by address 100. |
| 10 | Q5 | output | Latched active-high output 5. Selected by address 101. |
| 11 | Q6 | output | Latched active-high output 6. Selected by address 110. |
| 12 | Q7 | output | Latched active-high output 7. Selected by address 111. |
| 13 | D | input | Serial data input. Written into the addressed latch while G is low; in demultiplexer mode routed to the addressed output and inverted-then-forwarded through the internal decode network. |
| 14 | ~{G} | input | Active-low enable / write-strobe. When low, data at D is written into the latch selected by S2:S0. Hold high to freeze all latches (memory mode). |
| 15 | ~{CLR} | input | Active-low asynchronous clear. When low, forces all eight Q outputs low regardless of address, data, or G. Combines with G to select the four functional modes. |
| 16 | VCC | power_in | Positive supply, 2 V to 6 V (7 V absolute maximum). Bypass with 0.1 uF ceramic close to the pin. Quiescent ICC <= 80 uA typical. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
SN74HC259DRDSN74HC259DRSN74HC259DRNSN74HC259DRNSSN74HC259DRNSRSN74HC259DRPWSN74HC259DRPWRSN74HC259DRJSN74HC259DRFK
CAD (KiCad official)
- Symbol:
SN74HC259DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
bf1d352862715b29, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).