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SN74HC165DR

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by Ray

Texas Instruments Shift Registers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN74HC165DR

Texas Instruments · Shift Registers · SOP-16

SN74HC165DR from Texas Instruments, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Shift or Load control. When high, data is shifted on CLK rising edges. When low, the parallel A-H inputs are asynchronously loaded into the register.
2 CLK input Clock input. Data is shifted from A toward QH on a low-to-high transition while SH/LD is high and CLK INH is low. Interchangeable with CLK INH.
3 E input Parallel data input E. Loaded into stage E of the register when SH/LD is low.
4 F input Parallel data input F. Loaded into stage F of the register when SH/LD is low.
5 G input Parallel data input G. Loaded into stage G of the register when SH/LD is low.
6 H input Parallel data input H (last stage). Loaded into stage H when SH/LD is low; this bit appears at QH after loading.
7 ~{QH} output Complementary serial output. Inverted logic level of the H stage of the register. ±4 mA drive at 5 V.
8 GND power_in Ground reference (0 V).
9 QH output Serial output from the H stage of the register. Data shifted through the register appears here on each CLK rising edge. ±4 mA drive at 5 V.
10 SER input Serial data input. Data on SER is shifted into stage A on each CLK rising edge while SH/LD is high, enabling cascading of multiple '165 devices.
11 A input Parallel data input A (first stage). Loaded into stage A when SH/LD is low.
12 B input Parallel data input B. Loaded into stage B when SH/LD is low.
13 C input Parallel data input C. Loaded into stage C when SH/LD is low.
14 D input Parallel data input D. Loaded into stage D when SH/LD is low.
15 CLK_INH input Clock inhibit. When held high, clocking is disabled and the register output is unchanged. Must only transition low-to-high while CLK is high to avoid a spurious clock edge.
16 VCC power_in Positive supply, 2 V to 6 V recommended (7 V absolute maximum). Bypass with a local decoupling capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74HC165DRD
  • SN74HC165DR
  • SN74HC165DRDB
  • SN74HC165DRDBR
  • SN74HC165DRN
  • SN74HC165DRNS
  • SN74HC165DRNSR
  • SN74HC165DRPW
  • SN74HC165DRPWR
  • SN74HC165DRFK
  • SN74HC165DRJ
  • SN74HC165DRW

CAD (KiCad official)

  • Symbol: SN74HC165DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 517390062d4006fc, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF