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SN74ALS373ADWR

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by Ray

Texas Instruments Latches, SOIC-20-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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SN74ALS373ADWR

Texas Instruments · Latches · SOIC-20-300mil

SN74ALS373ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output-enable. When low, the Q outputs are in the enabled (normal logic) state; when high, all eight Q outputs are forced to high-impedance. Does not affect the internal latching operation. VIH = 2 V min, VIL = 0.8 V max at VCC = 5 V.
2 1Q tri_state Latch 1 3-state true output. Follows 1D while LE is high; holds last value when LE goes low; Hi-Z when OE is high. IOH = -2.6 mA, IOL = 24 mA at VCC = 4.5 V.
3 1D input Latch 1 data input. Sampled by latch 1 while LE is high (transparent) and captured on LE falling edge. pnp input reduces dc loading. Setup 10 ns, hold 7 ns.
4 2D input Latch 2 data input. Transparent while LE is high; captured on LE falling edge.
5 2Q tri_state Latch 2 3-state true output. Follows 2D when LE high; latched when LE low; Hi-Z when OE high.
6 3Q tri_state Latch 3 3-state true output. Follows 3D when LE high; latched when LE low; Hi-Z when OE high.
7 3D input Latch 3 data input. Transparent while LE is high; captured on LE falling edge.
8 4D input Latch 4 data input. Transparent while LE is high; captured on LE falling edge.
9 4Q tri_state Latch 4 3-state true output. Follows 4D when LE high; latched when LE low; Hi-Z when OE high.
10 GND power_in Device ground (0 V) reference for both logic and output drivers.
11 LE input Latch-enable input. While LE is high the Q outputs follow the D inputs (transparent); on the high-to-low transition of LE the D-input logic levels are latched. Minimum LE-high pulse duration 10 ns.
12 5Q tri_state Latch 5 3-state true output. Follows 5D when LE high; latched when LE low; Hi-Z when OE high.
13 5D input Latch 5 data input. Transparent while LE is high; captured on LE falling edge.
14 6D input Latch 6 data input. Transparent while LE is high; captured on LE falling edge.
15 6Q tri_state Latch 6 3-state true output. Follows 6D when LE high; latched when LE low; Hi-Z when OE high.
16 7Q tri_state Latch 7 3-state true output. Follows 7D when LE high; latched when LE low; Hi-Z when OE high.
17 7D input Latch 7 data input. Transparent while LE is high; captured on LE falling edge.
18 8D input Latch 8 data input. Transparent while LE is high; captured on LE falling edge.
19 8Q tri_state Latch 8 3-state true output. Follows 8D when LE high; latched when LE low; Hi-Z when OE high.
20 VCC power_in Positive supply voltage, 4.5 V to 5.5 V (5 V nominal). Bypass locally with a 0.1 uF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74ALS373ADWR
  • SN74ALS373ADWRN
  • SN74ALS373ADWRNSR
  • SN74ALS373ADWRDBR
  • SN74ALS373ADWRJ
  • SN74ALS373ADWRFK

CAD (KiCad official)

  • Symbol: SN74ALS373ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 0f5671f5caaf61ac, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF