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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

SN74AHCT595PWR

Texas Instruments · Shifting Register · TSSOP-16

SN74AHCT595PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QB	tri_state	Parallel 3-state output B from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
2	QC	tri_state	Parallel 3-state output C from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
3	QD	tri_state	Parallel 3-state output D from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
4	QE	tri_state	Parallel 3-state output E from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
5	QF	tri_state	Parallel 3-state output F from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
6	QG	tri_state	Parallel 3-state output G from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
7	QH	tri_state	Parallel 3-state output H (MSB) from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
8	GND	power_in	Ground reference. Connect to system 0 V.
9	QH'	output	Serial output from the last stage of the 8-bit shift register (not gated by OE). Used to cascade multiple '595 devices by connecting to the SER input of the next stage.
10	SRCLR	input	Active-low shift-register direct clear input. When low, asynchronously clears the 8-bit shift register (does not affect the storage register).
11	SRCLK	input	Shift-register clock input. On the rising edge, data at SER is shifted one bit into the 8-bit shift register (toward QH').
12	RCLK	input	Storage-register (latch) clock input. On the rising edge, the contents of the 8-bit shift register are transferred to the 8-bit storage register that drives QA..QH.
13	OE	input	Active-low output enable for QA..QH. When low, the storage-register outputs drive QA..QH; when high, QA..QH go to high-impedance. Does not affect QH'.
14	SER	input	Serial data input to the shift register. Sampled on the rising edge of SRCLK. Setup 3 ns, hold 2 ns before SRCLK rising edge.
15	QA	tri_state	Parallel 3-state output A (LSB) from the storage register. Drives up to IOH = -8 mA / IOL = 8 mA at VCC = 5 V. High-impedance when OE is high.
16	VCC	power_in	Positive supply, 4.5 V to 5.5 V recommended (7 V absolute maximum). Bypass with a 0.1 µF ceramic capacitor close to the pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

SN74AHCT595PWR
SN74AHCT595PWRBQB

CAD (KiCad official)

Symbol: SN74AHCT595PWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (32 pp, sha256 95659ecdcc6ac16c, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF