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Contents

README

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SN74AHC373PWR

Texas Instruments · Latches · TSSOP-20

SN74AHC373PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low Output Enable. When low, the eight Q outputs are enabled; when high, all Q outputs are placed in the high-impedance (3-state) condition. Does not affect the internal latch state.
2 1Q tri_state 3-state latched data output for channel 1. Follows 1D while LE is high; holds the latched value when LE is low; goes high-impedance when OE is high.
3 1D input D data input for channel 1. Latched into the flip-flop on the high-to-low transition of LE. CMOS input; VIH/VIL scale with VCC (2 V to 5.5 V).
4 2D input D data input for channel 2. Latched into the flip-flop on the high-to-low transition of LE.
5 2Q tri_state 3-state latched data output for channel 2. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
6 3Q tri_state 3-state latched data output for channel 3. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
7 3D input D data input for channel 3. Latched into the flip-flop on the high-to-low transition of LE.
8 4D input D data input for channel 4. Latched into the flip-flop on the high-to-low transition of LE.
9 4Q tri_state 3-state latched data output for channel 4. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
10 GND power_in Device ground reference (0 V). Return path for VCC supply and all input/output signals.
11 LE input Latch Enable. When high, the latches are transparent and Q outputs follow the D inputs. On the high-to-low transition of LE, the D data is latched and held on the Q outputs. Setup time (data before LE↓) 4 ns, hold time 1 ns, min pulse width 5 ns.
12 5Q tri_state 3-state latched data output for channel 5. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
13 5D input D data input for channel 5. Latched into the flip-flop on the high-to-low transition of LE.
14 6D input D data input for channel 6. Latched into the flip-flop on the high-to-low transition of LE.
15 6Q tri_state 3-state latched data output for channel 6. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
16 7Q tri_state 3-state latched data output for channel 7. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
17 7D input D data input for channel 7. Latched into the flip-flop on the high-to-low transition of LE.
18 8D input D data input for channel 8. Latched into the flip-flop on the high-to-low transition of LE.
19 8Q tri_state 3-state latched data output for channel 8. Transparent while LE is high, latched while LE is low, Hi-Z while OE is high.
20 VCC power_in Positive supply voltage. Recommended operating range 2 V to 5.5 V; absolute maximum 7 V. Bypass to GND with a 0.1 µF ceramic capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Ordering variants

Same part, different packaging or reel option.

  • SN74AHC373PWR
  • SN74AHC373PWRDW
  • SN74AHC373PWRDWR
  • SN74AHC373PWRDB
  • SN74AHC373PWRDBR
  • SN74AHC373PWRDGV
  • SN74AHC373PWRDGVR
  • SN74AHC373PWRN
  • SN74AHC373PWRNS
  • SN74AHC373PWRNSR
  • SN74AHC373PWRJ
  • SN74AHC373PWRW
  • SN74AHC373PWRFK

CAD (KiCad official)

  • Symbol: SN74AHC373PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74ahc373pwr.step 267 KB You want the bare part, or you mark your own boards.
sn74ahc373pwr-etched.step 3.0 MB You want the part with SN74AHC373PWR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 764 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 05f1299e78c443de, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF