SN74AHC123ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Channel 1 falling-edge trigger input (active-low A). Triggers a pulse on 1Q/1Q_bar when 1B=H; hold low for other input methods. Schmitt-trigger input.
2	1B	input	Channel 1 rising-edge trigger input (active-high B). Triggers a pulse on 1Q/1Q_bar when 1A=L; hold high for other input methods. Schmitt-trigger input.
3	1CLR	input	Channel 1 active-low overriding clear. Falling edge on 1CLR triggers a pulse when 1A=L and 1B=H; can cut pulse length short by driving low during output. Hold high for other input methods. Schmitt-trigger input.
4	1Q	output	Channel 1 inverted output (1Q_bar). CMOS push-pull output.
5	2Q	output	Channel 2 non-inverted output. CMOS push-pull output.
6	2Cext	passive	Channel 2 external timing capacitor negative terminal. Connect one lead of the external timing capacitor here; the other lead connects to 2Rext/Cext (pin 7).
7	2Rext/Cext	passive	Channel 2 external timing R/C junction. Connect the external timing resistor between this pin and VCC, and the external timing capacitor between this pin and 2Cext (pin 6). Rext min 5 kΩ at 2 V VCC, 1 kΩ at VCC > 3 V.
8	GND	power_in	Ground reference (0 V).
9	2A	input	Channel 2 falling-edge trigger input (active-low A). Triggers a pulse on 2Q/2Q_bar when 2B=H; hold low for other input methods. Schmitt-trigger input.
10	2B	input	Channel 2 rising-edge trigger input (active-high B). Triggers a pulse on 2Q/2Q_bar when 2A=L; hold high for other input methods. Schmitt-trigger input.
11	2CLR	input	Channel 2 active-low overriding clear. Falling edge on 2CLR triggers a pulse when 2A=L and 2B=H; can cut pulse length short by driving low during output. Hold high for other input methods. Schmitt-trigger input.
12	2Q	output	Channel 2 inverted output (2Q_bar). CMOS push-pull output.
13	1Q	output	Channel 1 non-inverted output. CMOS push-pull output.
14	1Cext	passive	Channel 1 external timing capacitor negative terminal. Connect one lead of the external timing capacitor here; the other lead connects to 1Rext/Cext (pin 15).
15	1Rext/Cext	passive	Channel 1 external timing R/C junction. Connect the external timing resistor between this pin and VCC, and the external timing capacitor between this pin and 1Cext (pin 14). Rext min 5 kΩ at 2 V VCC, 1 kΩ at VCC > 3 V.
16	VCC	power_in	Positive supply voltage, 2 V to 5.5 V. Bypass to GND with a 0.1 μF ceramic capacitor.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Ordering variants

Same part, different packaging or reel option.

SN74AHC123ADRD
SN74AHC123ADR
SN74AHC123ADRDB
SN74AHC123ADRPW
SN74AHC123ADRDGV
SN74AHC123ADRN
SN74AHC123ADRFK
SN74AHC123ADRJ
SN74AHC123ADRW

CAD (KiCad official)

Symbol: SN74AHC123ADR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (36 pp, sha256 1a0b625278e7d4c2, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF