component
sn74act74dr
Public Unreviewedby Ray
Texas Instruments Flip Flops, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSN74ACT74DR
Texas Instruments · Flip Flops · SOIC-14
SN74ACT74DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Channel 1 asynchronous clear input, active low. Drives Q low and Q̄ high independent of clock and data. TTL-compatible; VIH ≥ 2V, VIL ≤ 0.8V; input voltage tolerated to 5.5V. |
| 2 | 1D | input | Channel 1 data input. Sampled on the rising edge of 1CLK subject to setup/hold. TTL-compatible input, 5.5V tolerant. |
| 3 | 1CLK | input | Channel 1 positive-edge-triggered clock input. Data on 1D is transferred to 1Q on the rising edge. Max clock frequency 125 MHz (SN74 grade); TTL-compatible, 5.5V tolerant. |
| 4 | 1PRE | input | Channel 1 asynchronous preset input, active low. Drives Q high and Q̄ low independent of clock and data. TTL-compatible; 5.5V tolerant. |
| 5 | 1Q | output | Channel 1 true output. CMOS push-pull; rated ±24 mA at 5V; VOH ≥ 4.4V and VOL ≤ 0.44V at rated current. |
| 6 | 1Q_N | output | Channel 1 complementary (inverted) output. CMOS push-pull; rated ±24 mA at 5V. Labeled 1Q̄ in the datasheet. |
| 7 | GND | power_in | Device ground reference. Connect to the system 0V rail. |
| 8 | 2Q_N | output | Channel 2 complementary (inverted) output. CMOS push-pull; rated ±24 mA at 5V. Labeled 2Q̄ in the datasheet. |
| 9 | 2Q | output | Channel 2 true output. CMOS push-pull; rated ±24 mA at 5V; VOH ≥ 4.4V and VOL ≤ 0.44V at rated current. |
| 10 | 2PRE | input | Channel 2 asynchronous preset input, active low. Drives 2Q high and 2Q̄ low independent of clock and data. TTL-compatible; 5.5V tolerant. |
| 11 | 2CLK | input | Channel 2 positive-edge-triggered clock input. Data on 2D is transferred to 2Q on the rising edge. Max clock frequency 125 MHz (SN74 grade); TTL-compatible, 5.5V tolerant. |
| 12 | 2D | input | Channel 2 data input. Sampled on the rising edge of 2CLK subject to setup/hold. TTL-compatible input, 5.5V tolerant. |
| 13 | 2CLR | input | Channel 2 asynchronous clear input, active low. Drives 2Q low and 2Q̄ high independent of clock and data. TTL-compatible; 5.5V tolerant. |
| 14 | VCC | power_in | Positive supply, 4.5V to 5.5V. Bypass locally with a 0.1 µF ceramic capacitor to GND close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
SN74ACT74DRSN74ACT74DRDSN74ACT74DRPWSN74ACT74DRPWRSN74ACT74DRDBSN74ACT74DRDBRSN74ACT74DRNSN74ACT74DRNSSN74ACT74DRNSRSN74ACT74DRBQASN74ACT74DRBQARSN74ACT74DRFKSN74ACT74DRJSN74ACT74DRW
CAD (KiCad official)
- Symbol:
SN74ACT74DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (None pp, sha256
16c999e19ba23c81, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).