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SN65LVDS315RGER

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by Ray

Texas Instruments Serializers, Deserializers, VQFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDS315RGER

Texas Instruments · Serializers, Deserializers · VQFN-24-EP(4x4)

SN65LVDS315RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GNDD power_in Digital supply ground for VDDIO and VDDD. Tie to common ground plane.
2 DOUT+ output SubLVDS data link CSI-1 compliant positive output. Active during normal operation; high-impedance during power down or standby. DOUT is valid on the rising edge of CLK+.
3 DOUT- output SubLVDS data link CSI-1 compliant negative output. Active during normal operation; high-impedance during power down or standby.
4 CLK+ output SubLVDS clock output positive (CSI-1 Mode 0 compliant). Serial clock accompanying DOUT differential data.
5 CLK- output SubLVDS clock output negative (CSI-1 Mode 0 compliant).
6 GNDA power_in PLL and SubLVDS analog ground. Tie to common ground plane.
7 TXEN input Transmitter enable. TXEN=1 enables the SubLVDS drivers and PLL; TXEN=0 disables them (shutdown mode). Incorporates glitch-suppression logic requiring the input to be held >10 µs to register. Do not leave floating. Referenced to VDDIO (1.8-3.3 V).
8 MODE input MODE selects line-counting behavior for EOF signalling when VS and HS do not reset during the same DCLK cycle (0 = line counter disabled; 1 = counter enabled). TI recommends MODE=high when unsure. Do not leave floating.
9 VDDA power_in PLL and SubLVDS I/O analog supply (1.8 V only). Bypass locally to GNDA.
10 D0 input Parallel pixel data input bit 0 (LSB). Sampled on the falling DCLK edge; latched into the device on that edge. CMOS input with bus hold, referenced to VDDIO (1.65-3.6 V range).
11 D1 input Parallel pixel data input bit 1. Sampled on the falling DCLK edge. CMOS input with bus hold.
12 D2 input Parallel pixel data input bit 2. Sampled on the falling DCLK edge. CMOS input with bus hold.
13 D3 input Parallel pixel data input bit 3. Sampled on the falling DCLK edge. CMOS input with bus hold.
14 D4 input Parallel pixel data input bit 4. Sampled on the falling DCLK edge. CMOS input with bus hold.
15 D5 input Parallel pixel data input bit 5. Sampled on the falling DCLK edge. CMOS input with bus hold.
16 DCLK input Data input clock; represents the camera pixel clock. All 8 pixel bits, VS and HS are latched on the falling edge of DCLK. Supports 3.5-13 MHz (FSEL=0) or 7-27 MHz (FSEL=1). CMOS input with bus hold.
17 GNDD power_in Digital supply ground for VDDIO and VDDD. Second GNDD pin; tie to ground plane.
18 D6 input Parallel pixel data input bit 6. Sampled on the falling DCLK edge. CMOS input with bus hold.
19 D7 input Parallel pixel data input bit 7 (MSB). Sampled on the falling DCLK edge. CMOS input with bus hold.
20 VS input Vertical Sync (also called frame sync). High-active data input sampled on every falling DCLK edge. CMOS input with bus hold, referenced to VDDIO.
21 HS input Horizontal Sync (also called line sync). High-active data input sampled on every falling DCLK edge. CMOS input with bus hold, referenced to VDDIO.
22 VDDIO power_in I/O supply voltage for the CMOS inputs D[0:7], HS, VS and DCLK. Supports 1.8 V to 3.3 V to match the host/camera GPIO rail.
23 VDDD power_in Digital core supply voltage (1.8 V only). Bypass locally to GNDD.
24 FSEL input Frequency Select. FSEL=0 selects DCLK range 3.5-13 MHz; FSEL=1 selects DCLK range 7-27 MHz. Do not leave floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Interface
Pins 24

Ordering variants

Same part, different packaging or reel option.

  • SN65LVDS315RGER
  • SN65LVDS315RGERRGET

CAD (KiCad official)

  • Symbol: SN65LVDS315RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 c6311404a0aac6c9, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF