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SN65LV1023ADB

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by Ray

Texas Instruments Serializers, Deserializers, SSOP-28. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN65LV1023ADB

Texas Instruments · Serializers, Deserializers · SSOP-28

SN65LV1023ADB from Texas Instruments, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC1 input LVTTL logic input. SYNC1 and SYNC2 are ORed together. Asserting either high for six TCLK cycles initiates transmission of 1026 SYNC patterns to allow the deserializer to lock.
2 SYNC2 input LVTTL logic input. SYNC1 and SYNC2 are ORed together. Asserting either high for six TCLK cycles initiates transmission of 1026 SYNC patterns to allow the deserializer to lock.
3 DIN0 input Parallel LVTTL data input, bit 0.
4 DIN1 input Parallel LVTTL data input, bit 1.
5 DIN2 input Parallel LVTTL data input, bit 2.
6 DIN3 input Parallel LVTTL data input, bit 3.
7 DIN4 input Parallel LVTTL data input, bit 4.
8 DIN5 input Parallel LVTTL data input, bit 5.
9 DIN6 input Parallel LVTTL data input, bit 6.
10 DIN7 input Parallel LVTTL data input, bit 7.
11 DIN8 input Parallel LVTTL data input, bit 8.
12 DIN9 input Parallel LVTTL data input, bit 9.
13 TCLK_R/F input LVTTL logic input selecting the TCLK edge used to strobe parallel data. Low = falling-edge strobe; high = rising-edge strobe.
14 TCLK input LVTTL-level reference clock input, 10 MHz to 66 MHz. Strobes parallel data into the input latch and provides the PLL reference. Serial output rate is 12 x TCLK.
15 DGND power_in Digital circuit ground return.
16 DGND power_in Digital circuit ground return.
17 AVCC power_in Analog circuit power supply for the PLL and analog circuits. 3.0 V to 3.6 V (nom 3.3 V).
18 AGND power_in Analog circuit ground return for the PLL and analog circuits.
19 DEN input LVTTL data enable input. Low forces the LVDS serial output (DO+/DO-) into high-impedance state; high enables the serial data output.
20 AGND power_in Analog circuit ground return for the PLL and analog circuits.
21 DO- output Inverting LVDS differential serial data output. Nominal 350-450 mV differential swing across a 100 Ω line (27 Ω test load per datasheet).
22 DO+ output Noninverting LVDS differential serial data output. Nominal 350-450 mV differential swing across a 100 Ω line (27 Ω test load per datasheet).
23 AGND power_in Analog circuit ground return for the PLL and analog circuits.
24 PWRDN input Active-low LVTTL power-down input (overbar in datasheet). Low turns off the PLL, forces the outputs into high-impedance, and places the device into low-power mode.
25 AGND power_in Analog circuit ground return for the PLL and analog circuits.
26 AVCC power_in Analog circuit power supply for the PLL and analog circuits. 3.0 V to 3.6 V (nom 3.3 V).
27 DVCC power_in Digital circuit power supply. 3.0 V to 3.6 V (nom 3.3 V). DVCC and AVCC are internally separated.
28 DVCC power_in Digital circuit power supply. 3.0 V to 3.6 V (nom 3.3 V). DVCC and AVCC are internally separated.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-28
Category Interface
Pins 28

Ordering variants

Same part, different packaging or reel option.

  • SN65LV1023ADB
  • SN65LV1023ADBRHB

CAD (KiCad official)

  • Symbol: SN65LV1023ADB
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 4bd91afc862e7bca, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF