component
sn65hvd233dr-jsm
Public Unreviewedby Ray
JSMSEMI CAN Transceivers, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownSN65HVD233DR-JSM
JSMSEMI · CAN Transceivers · SOP-8
SN65HVD233DR-JSM from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | input | CAN transmit data input (TXD). LOW drives a dominant bus state; HIGH (or open) leaves the bus in the recessive state. LVTTL input, withstands up to 5V. Should be biased with an external 1kΩ-10kΩ pull-up if driven by an open-drain host. |
| 2 | GND | power_in | Ground / network reference. All voltages except differential bus voltages are referenced to this pin. |
| 3 | VCC | power_in | Transceiver 3.3V supply (recommended 3.0V-3.6V). Decouple with a 100 nF ceramic capacitor placed as close to the pin as possible. |
| 4 | R | output | CAN receive data output (RXD). LOW for a dominant bus state; HIGH for a recessive bus state. VOH ≥ 2.4V at IO = -4 mA; VOL ≤ 0.4V at IO = 4 mA. |
| 5 | LBK | input | Mode-select input for the SN65HVD233. Logic HIGH enables diagnostic (internal) loopback: the driver output is disabled (bus held recessive) while the D→R internal path stays active for self-diagnostics. LOW enables normal transmit/receive operation. Internally pulled low; may be left open if unused. LVTTL input, withstands up to 5V. |
| 6 | CANL | bidirectional | Low-side CAN differential bus I/O. Driven low (~1V) during a dominant state and biased to VCC/2 (recessive) otherwise. Withstands ±40V bus faults and -7V to 12V common-mode range; ±16 kV HBM ESD. |
| 7 | CANH | bidirectional | High-side CAN differential bus I/O. Driven high (~3V) during a dominant state and biased to VCC/2 (recessive) otherwise. Withstands ±40V bus faults and -7V to 12V common-mode range; ±16 kV HBM ESD. |
| 8 | RS | input | Mode-select / slope-control pin. Strong pull-down to GND (0Ω) selects high-speed mode; a 10kΩ-100kΩ resistor to GND sets slope-control mode (slew rate ~15 V/µs at 10kΩ, ~10 V/µs at 100kΩ); a strong pull-up (> 0.75·VCC) selects low-power listen-only standby mode (driver off, receiver active, ICC ≈ 400 µA typ). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-8 |
| Category | Interface |
| Pins | 8 |
Ordering variants
SN65HVD233DR-JSMSN65HVD233DR-JSMSN65HVD234DRSN65HVD233DR-JSMSN65HVD235DR
CAD (KiCad official)
- Symbol:
SN65HVD233DR-JSM - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (None pp, sha256
5860e58946d38d57, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).