SL2.1s from CoreChips, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DM2	bidirectional	Downstream Port 2 USB D- data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
2	DP2	bidirectional	Downstream Port 2 USB D+ data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
3	DM1	bidirectional	Downstream Port 1 USB D- data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
4	DP1	bidirectional	Downstream Port 1 USB D+ data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
5	UDM	bidirectional	Upstream port USB D- data line to the host. Integrated 1.5 kΩ pull-up (Rpu) and 45 Ω high-speed termination (Rs).
6	UDP	bidirectional	Upstream port USB D+ data line to the host. Integrated 1.5 kΩ pull-up (Rpu) and 45 Ω high-speed termination (Rs).
7	VCC5	power_in	5 V main supply input. Feeds the internal 5V→3.3V LDO that drives VDD33.
8	VSS	power_in	Chip ground reference (0 V).
9	VDD33	power_out	3.3 V LDO output. Must be bypassed with a 4.7 µF capacitor to ground placed close to the pin; also feeds the analog 3.3 V rail internally via the PCB.
10	VDD18	power_out	Digital 1.8 V LDO output. Must be bypassed with a 4.7 µF capacitor to ground placed close to the pin.
11	XOUT	output	12 MHz crystal oscillator output pin. Connect to a 12 MHz crystal (CL=20 pF, ≥20 ppm); no external load capacitors required per datasheet §3.3.
12	XIN	input	12 MHz crystal oscillator input pin. Connect to a 12 MHz crystal (CL=20 pF, ≥20 ppm).
13	DM4	bidirectional	Downstream Port 4 USB D- data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
14	DP4	bidirectional	Downstream Port 4 USB D+ data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
15	DM3	bidirectional	Downstream Port 3 USB D- data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).
16	DP3	bidirectional	Downstream Port 3 USB D+ data line. Integrated 15 kΩ pull-down (Rpd) and 45 Ω high-speed termination (Rs).

Key specifications

Parameter	Value
Manufacturer	CoreChips
Package	SSOP-16
Category	Interface
Pins	16

Ordering variants

Same part, different packaging or reel option.

SL2.1S
SL2.1A
SL2.2S
SL2.2Q

CAD (KiCad official)

Symbol: SL2.1s
Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
3D model: SSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sl2-1s.step`	217 KB	You want the bare part, or you mark your own boards.
`sl2-1s-etched.step`	1.8 MB	You want the part with `SL2.1s` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 449 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CoreChips datasheet (21 pp, sha256 9a55c6649643b949, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF