SIT3485EESA from SIT, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RO	output	Receiver Output. With /RE low, RO goes high when (A − B) ≥ −10 mV and low when (A − B) ≤ −200 mV. RO is high-impedance when /RE is high. CMOS output, VOH ≥ VCC − 1.5 V at IOUT = −2.5 mA.
2	/RE	input	Receiver Output Enable (active-low). Drive /RE low to enable RO; RO is high-impedance when /RE is high. Driving /RE high together with DE low enters low-power shutdown (ISHDN ≈ 0.2 µA typ).
3	DE	input	Driver Output Enable (active-high). Drive DE high to enable the A/B driver outputs; the outputs are high-impedance when DE is low. Driving DE low together with /RE high enters low-power shutdown mode.
4	DI	input	Driver Input. With DE high, a low on DI forces the non-inverting driver output (A) low and the inverting output (B) high; a high on DI drives A high and B low. CMOS logic level (VIH ≥ 2.0 V, VIL ≤ 0.8 V).
5	GND	power_in	Ground reference for logic and driver/receiver circuitry.
6	A	bidirectional	Non-inverting Receiver Input and non-inverting Driver Output (RS-485/RS-422 bus line A). Withstands ±15 V bus fault, tolerates −7 V to +12 V common-mode range, ±15 kV HBM ESD protection, 96 kΩ minimum input resistance (1/8 unit load).
7	B	bidirectional	Inverting Receiver Input and inverting Driver Output (RS-485/RS-422 bus line B). Withstands ±15 V bus fault, tolerates −7 V to +12 V common-mode range, ±15 kV HBM ESD protection, 96 kΩ minimum input resistance (1/8 unit load).
8	VCC	power_in	Positive supply, 3.0 V to 5.5 V (absolute max +7 V). Typical supply current 240 µA at 3.3 V / 270 µA at 5 V; shutdown current ~0.2 µA typ.

Key specifications

Parameter	Value
Manufacturer	SIT
Package	SOIC-8
Category	Comm/UART
Pins	8

Ordering variants

Same part, different packaging or reel option.

SIT3485EESA
SIT3485EEUA
SIT3485EEPA

CAD (KiCad official)

Symbol: SIT3485EESA
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`sit3485eesa.step`	122 KB	You want the bare part, or you mark your own boards.
`sit3485eesa-etched.step`	2.4 MB	You want the part with `SIT3485EESA` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 584 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SIT datasheet (14 pp, sha256 2d7a48dfb8201639, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF