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SI53358A-D01AM

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by Ray

SKYWORKS SILICON LABS Clock Buffers, Drivers, Distributors, QFN-40-EP(6x6). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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SI53358A-D01AM

SKYWORKS SILICON LABS · Clock Buffers, Drivers, Distributors · QFN-40-EP(6x6)

SI53358A-D01AM from SKYWORKS SILICON LABS, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD_DIG power_in Voltage supply for digital functions, connect to 1.8-3.3 V, must be connected to same voltage as VDDA and VDD.
2 CLKIN_1 input Clock input 1 accepting differential or single-ended clock signals at 10-250 MHz, high-impedance input requiring external termination.
3 CLKIN_1b input Differential pair for clock input 1 accepting differential or single-ended clock signals at 10-250 MHz, high-impedance input requiring external termination.
4 VDD power_in Voltage supply, connect to 1.8-3.3 V, must be connected to same voltage as VDDA and VDD_DIG.
5 NC unconnected Do not connect.
6 NC unconnected Do not connect.
7 CLKIN_2 input Clock input 2 accepting differential or single-ended clock signals at 10-250 MHz, high-impedance input requiring external termination.
8 CLKIN_2b input Differential pair for clock input 2 accepting differential or single-ended clock signals at 10-250 MHz, high-impedance input requiring external termination.
9 VDDA power_in Core supply voltage, connect to 1.8-3.3 V, must be connected to same voltage as VDD_DIG and VDD.
10 Format_SEL0 input Output clock format selection pin used with pin 19 to select LVCMOS, LVPECL, LVDS, or HCSL output format.
11 GND power_in Connect to ground.
12 GND power_in Connect to ground.
13 OUT0b output Differential output clock 0 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
14 OUT0 output Differential output clock 0 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
15 VDDO0 power_in Supply voltage for OUT0, connect to 1.8-3.3 V, leave unconnected if output is unused.
16 OUT1b output Differential output clock 1 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
17 OUT1 output Differential output clock 1 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
18 VDDO1 power_in Supply voltage for OUT1, connect to 1.8-3.3 V, leave unconnected if output is unused.
19 Format_SEL1 input Output clock format selection pin used with pin 10 to select LVCMOS, LVPECL, LVDS, or HCSL output format.
20 Input_SEL input Input clock selection pin, logic 0 selects CLKIN_1/CLKIN_1b, logic 1 selects CLKIN_2/CLKIN_2b.
21 OUT2b output Differential output clock 2 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
22 OUT2 output Differential output clock 2 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
23 OUT3b output Differential output clock 3 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
24 OUT3 output Differential output clock 3 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
25 VDDO2 power_in Supply voltage for OUT2 and OUT3, connect to 1.8-3.3 V, leave unconnected if outputs are unused.
26 OUT4b output Differential output clock 4 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
27 OUT4 output Differential output clock 4 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
28 VDDO3 power_in Supply voltage for OUT4 and OUT5, connect to 1.8-3.3 V, leave unconnected if outputs are unused.
29 OUT5b output Differential output clock 5 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
30 OUT5 output Differential output clock 5 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
31 OEb_OUT[1:0] input Output enable for OUT0 and OUT1, logic 0 enables outputs, logic 1 disables outputs.
32 OEb_OUT[3:2] input Output enable for OUT2 and OUT3, logic 0 enables outputs, logic 1 disables outputs.
33 VDDO4 power_in Supply voltage for OUT6, connect to 1.8-3.3 V, leave unconnected if output is unused.
34 OUT6b output Differential output clock 6 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
35 OUT6 output Differential output clock 6 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
36 OEb_OUT[5:4] input Output enable for OUT4 and OUT5, logic 0 enables outputs, logic 1 disables outputs.
37 OEb_OUT[7:6] input Output enable for OUT6 and OUT7, logic 0 enables outputs, logic 1 disables outputs.
38 OUT7b output Differential output clock 7 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
39 OUT7 output Differential output clock 7 supporting programmable signal swing and common mode voltage at 10-250 MHz, leave unconnected if unused.
40 VDDO5 power_in Supply voltage for OUT7, connect to 1.8-3.3 V, leave unconnected if output is unused.
41 Ground power_in Center ground pad providing electrical and thermal connection to ground, must be connected for proper operation.

Key specifications

Parameter Value
Manufacturer SKYWORKS SILICON LABS
Package QFN-40-EP(6x6)
Category Clock/Timing
Pins 41

CAD (KiCad official)

  • Symbol: SI53358A-D01AM
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SKYWORKS SILICON LABS datasheet (63 pp, sha256 c46ddd6abc7831e4, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF