SI522 from Nanjing Zhongke Microelectronics, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDI	input	Serial Data Interface (2-wire) enable input. Held high (with EA) to select the 2-wire serial host interface after reset; part of the interface auto-detect strap set.
2	PVDD	power_in	Pin (pad-driver) power supply, 2.5 V to 3.6 V (recommended 3.3 V). PVDD must be less than or equal to DVDD.
3	DVDD	power_in	Digital core power supply, 2.5 V to 3.6 V (typ. 3.3 V). Must be tied to the same rail as VDDA and TVDD per note 1 in 表 4-2.
4	DVSS	power_in	Digital ground reference (0 V). The QFN exposed thermal pad on the package underside must be connected to DVSS.
5	PVSS	power_in	Pin (pad-driver) ground reference (0 V) for the PVDD domain.
6	NRSTPD	input	Reset and hard power-down input. Driving low enters hard power-down: internal current sinks and oscillator are disabled and the input pins are disconnected. A rising edge releases reset.
7	MFIN	input	Factory/test input (measurement input). Not used in normal operation.
8	MFOUT	output	Factory/test output (measurement output). Not used in normal operation.
9	SVDD	power_in	Supply for the MFIN/MFOUT test-pin pad drivers, 2.5 V to 3.6 V (typ. 3.3 V).
10	TVSS	power_in	Transmitter output-stage 1 ground return (high-current). Tie to the low-impedance analog ground plane close to the antenna matching network.
11	TX1	output	Transmitter 1 output: 13.56 MHz modulated carrier driver output for the reader antenna (differential with TX2).
12	TVDD	power_in	Transmitter supply for the TX1 and TX2 output stages, 2.5 V to 3.6 V (typ. 3.3 V). Sets the drive amplitude into the antenna.
13	TX2	output	Transmitter 2 output: 13.56 MHz modulated carrier driver output for the reader antenna (differential with TX1).
14	TVSS	power_in	Transmitter output-stage 2 ground return (high-current). Tie to the low-impedance analog ground plane close to the antenna matching network.
15	AVDD	power_in	Analog supply for the receiver and reference circuitry, 2.5 V to 3.6 V (typ. 3.3 V). IDDA is 2.9 mA typ. with receiver active, 0.8 mA typ. with RcvOff=1.
16	VMID	passive	Internal analog reference voltage node. Decouple with an external capacitor to AVSS; do not load externally.
17	RX	input	Receiver RF input from the antenna matching / receive network. Feeds the on-chip demodulator/decoder.
18	AVSS	power_in	Analog ground reference (0 V) for the AVDD/VMID/RX domain.
19	AUX1	output	Auxiliary analog/digital test output for factory characterization. Leave unconnected in normal use.
20	AUX2	output	Auxiliary analog/digital test output for factory characterization. Leave unconnected in normal use.
21	OSCIN	input	Crystal oscillator inverting amplifier input; also accepts an externally generated 27.12 MHz clock reference (fclk = 27.12 MHz).
22	OSCOUT	output	Crystal oscillator inverting amplifier output. Connect to the second terminal of the 27.12 MHz crystal; leave floating when driving OSCIN from an external clock.
23	IRQ	output	Interrupt request output to the host controller. Asserts to indicate an interrupt event; polarity/behavior configured via the interrupt registers.
24	SD/NSS/RX	bidirectional	Multiplexed host-interface pin. As SD: bidirectional data line for the 2-wire serial interface. As NSS: SPI chip-select input (active-low). As RX: UART data input from host to Si522.
25	D1/ADR_5	bidirectional	Multiplexed. D1: test port I/O (SPI/UART modes leave it unused, tie per app note). ADR_5: 2-wire serial address bit 5 input when the 2-wire interface is selected.
26	D2/ADR_4	bidirectional	Multiplexed. D2: test port I/O (unused in SPI/UART modes). ADR_4: 2-wire serial address bit 4 input.
27	D3/ADR_3	bidirectional	Multiplexed. D3: test port I/O (unused in SPI/UART modes). ADR_3: 2-wire serial address bit 3 input.
28	D4/ADR_2	bidirectional	Multiplexed. D4: test port I/O (unused in SPI/UART modes). ADR_2: 2-wire serial address bit 2 input.
29	D5/ADR_1/SCK/DTRQ	bidirectional	Multiplexed. SCK: SPI serial clock input from the host (up to 10 MHz). DTRQ: UART request-to-send output to the host. ADR_1: 2-wire address bit 1 input. D5: factory test I/O.
30	D6/ADR_0/MOSI/MX	bidirectional	Multiplexed. MOSI: SPI master-out/slave-in data input. MX: UART data output from Si522 to host. ADR_0: 2-wire address bit 0 input. D6: factory test I/O.
31	D7/SC/MISO/TX	bidirectional	Multiplexed. MISO: SPI master-in/slave-out data output. TX: UART data output from Si522 to host. SC: 2-wire serial clock I/O. D7: factory test I/O.
32	EA	input	External address input strap for the 2-wire serial interface. Also part of the interface auto-detect: EA=0 with SDI=0 selects UART, EA=1 with SDI=0 selects SPI, and EA is used as the encoded address bit when the 2-wire interface is selected.

Key specifications

Parameter	Value
Manufacturer	Nanjing Zhongke Microelectronics
Package	QFN-32-EP(5x5)
Category	RF And Wireless
Pins	32

CAD (KiCad official)

Symbol: SI522
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nanjing Zhongke Microelectronics datasheet (38 pp, sha256 94296fadef3b08d9, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF