component
SI3404-A-GMR
Public Unreviewedby Ray
SKYWORKS SILICON LABS Power Over Ethernet (PoE) Controllers, QFN-20-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.
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markdownSI3404-A-GMR
SKYWORKS SILICON LABS · Power Over Ethernet (PoE) Controllers · QFN-20-EP(4x4)
SI3404-A-GMR from SKYWORKS SILICON LABS, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ISNS | input | Average current-sense resistor input for the dc-dc converter. Sets the maximum allowed current via external sense resistor; the overcurrent threshold voltage is V_ISNS_OVC. Note this pin voltage can go below VSS. Vrange: -0.5 to 0 V, referenced to VSS. |
| 2 | FBH | input | High-side (VPOS-referenced) dc-dc feedback input, used for buck converter topology. Tie to VPOS when not used. Vrange: 0-5.5 V, referenced to VPOS. |
| 3 | EROUT | bidirectional | Error amplifier current output for the dc-dc converter; loop compensation impedance is connected here. I_EROUT = (V_FBH - V_FBREF) x 50 uA or (V_FBL - V_FBREF) x 50 uA. Vrange: 0-5.5 V, referenced to VSS. |
| 4 | FBL | input | Low-side (VSS-referenced) dc-dc feedback input, used for flyback converter topology. Tie to VSS when not used. Vrange: 0-5.5 V, referenced to VSS. |
| 5 | VDD | power_out | Regulated 5 V output relative to VSS. Powers internal logic; requires external C_REG bypass capacitance. No foldback characteristic; output voltage decreases when reaching VDD_ILIM. Vrange: 0-5.5 V. |
| 6 | RDET | bidirectional | Detection signature resistor pin. External R_DET is tied between this pin and VPOS to present the ~25 kOhm PoE detection signature. During detection a high-voltage switch pulls RDET to VNEG; after detection the reference block forces -750 mV vs VPOS to create 30 uA for internal blocks. Vrange: 0-100 V referenced to VPOS. |
| 7 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| 8 | HSO | bidirectional | Hotswap switch output. Internal high-voltage hotswap FET shorts VNEG to HSO when enabled, with inrush current limiting and overcurrent protection. Vrange: 0-100 V referenced to VNEG. |
| 9 | RCL | bidirectional | Classification resistor input. External R_EXT sets PoE class current; pin is active only during PoE classification. For Class 0 this pin may be left floating. Vrange: 0-5.5 V referenced to VNEG. |
| 10 | RFREQ | bidirectional | Oscillator frequency tuning resistor pin. External resistor from RFREQ to VPOS sets the dc-dc switching frequency (100-500 kHz, inversely proportional to R). Tie directly to VPOS to select the default 250 kHz. Vrange: 0-5.5 V referenced to VPOS. |
| 11 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| 12 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| 13 | VPOS | power_in | Rectified high-voltage supply positive rail from the PoE bridge; main chip input power. Vrange: 0-100 V. Absolute max 120 V. |
| 14 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| 15 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| 16 | VT15 | input | Optional 15 V auxiliary transformer bias-winding input. If bias-winding voltage falls below V_T15_MIN, the internal 15 V coarse regulator supplies the internal 11 V regulator. Vrange: 0-16.5 V referenced to VSS. |
| 17 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| 18 | SWO | output | Internal dc-dc switching NMOS transistor drain output. Vmax = 120 V. Connects to the switching-converter inductor/transformer primary. Vrange: 0-120 V referenced to VSS. |
| 19 | VSS | power_in | dc-dc converter primary ground. Reference for internal analog and dc-dc converter circuitry (distinct from VNEG PoE-input ground). |
| 20 | NC | unconnected | No internal connection. Connect to VNEG for better thermal performance. |
| EP | VNEG | power_in | Exposed thermal pad; rectified high-voltage supply ground (PoE line-side negative return). Also provides the primary thermal relief path and must be soldered to the PCB ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS SILICON LABS |
| Package | QFN-20-EP(4x4) |
| Category | PMIC |
| Pins | 21 |
Ordering variants
Same part, different packaging or reel option.
SI3404-A-GMRSi3404-A-GMR
CAD (KiCad official)
- Symbol:
SI3404-A-GMR - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SKYWORKS SILICON LABS datasheet (26 pp, sha256
58b4022c78aa84e6, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).