SGM6132YPS8G
Public Unreviewedby Ray
SGMICRO DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownSGM6132YPS8G
SGMICRO · DC-DC Converters · SOIC-8-EP
SGM6132YPS8G from SGMICRO, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | High-side Gate Drive Boost Input. BS supplies the driver for the high-side N-channel MOSFET switch. Connect a 10nF or greater capacitor from SW to BS to bootstrap the high-side switch. A 10Ω resistor between SW and the BS cap is strongly recommended to reduce SW spike voltage. |
| 2 | IN | power_in | Power Input. Supplies power to the IC and the step-down converter switches. Drive with a 4.5V to 28.5V source. Bypass IN to GND with a sufficiently large capacitor (22µF ceramic recommended) to eliminate input noise. |
| 3 | SW | power_out | Power Switching Output. Switching node that supplies power to the output. Connect the output LC filter from SW to the load. A bootstrap capacitor is required from SW to BS to power the high-side switch. |
| 4 | GND | power_in | Ground. The exposed pad on the backside must be connected to pin 4 and tied to the GND plane for proper thermal and electrical performance. |
| 5 | FB | input | Feedback Input. The voltage at this pin is regulated to 0.8V (typ). Connect to the resistor divider between output and ground to set the output voltage. |
| 6 | COMP | output | Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network from COMP to GND to compensate the loop; in some cases an additional capacitor from COMP to GND is required. |
| 7 | EN | input | Enable Input. Digital input that turns the regulator on (VIH ≥ 1.2V) or off (VIL ≤ 0.4V). When EN is low the output is discharged and the IC is off. Has an internal ~1.4µA pull-up current so leaving EN unconnected causes automatic startup. |
| 8 | SS | passive | Soft-Start Control Input. Connect a capacitor from SS to GND to set the soft-start period; a 0.1µF capacitor sets ≈10ms soft-start. Leave SS unconnected to disable the soft-start feature. |
| EP | GND | power_in | Power Ground Exposed Pad. Must be connected to the GND plane and tied to pin 4 for thermal dissipation and ground return. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SGMICRO |
| Package | SOIC-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SGM6132YPS8G/TR
CAD (KiCad official)
- Symbol:
SGM6132YPS8G - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sgm6132yps8g.step |
125 KB | You want the bare part, or you mark your own boards. |
sgm6132yps8g-etched.step |
2.9 MB | You want the part with SGM6132YPS8G already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 688 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SGMICRO datasheet (14 pp, sha256
d83cfb4e5526354d, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).