component
SCT2452STER
Public Unreviewedby Ray
SCT DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSCT2452STER
SCT · DC-DC Converters · ESOP-8
SCT2452STER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap supply for high-side power MOSFET gate driver. Connect a 0.1µF capacitor between BOOT and SW; the bootstrap cap is charged when the low-side MOSFET is on or SW is low. BOOT-SW UVLO threshold ≈ 2.36V. |
| 2 | VIN | power_in | Input supply voltage, 3.8V to 36V (42V transient max). Connect a local high-frequency bypass capacitor from VIN to GND as close as possible to the pin. |
| 3 | EN | input | Enable input with internal pull-up current source (~1.5µA at 1V). Pull below 1.1V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold (VEN_H ≈ 1.18V). |
| 4 | RT/CLK | bidirectional | Sets internal oscillator frequency or accepts an external clock. Resistor to GND programs Fsw from 100kHz to 1.1MHz (e.g. 200kΩ ≈ 500kHz); alternatively drive with an external clock (100kHz-1.1MHz) for PLL synchronization. Reverts to resistor-programmed frequency if the external clock stops. |
| 5 | FB | input | Inverting input of the transconductance error amplifier. Connect a resistor divider from VOUT to FB to GND; the loop regulates FB to VREF = 0.8V (typ, ±1%). Overvoltage protection trips at ~110% of VREF. |
| 6 | SS | passive | Soft-start programming pin. Connect a capacitor from SS to GND; internal ~3µA source current charges it to set the output voltage ramp time. |
| 7 | GND | power_in | Device ground. Common return for input bypass, output feedback, and control-circuit references. |
| 8 | SW | power_out | Switch node - regulator switching output. Connect to the external power inductor. Absolute range -1V to 38V; also the bootstrap capacitor return for the high-side driver. |
| 9 | Thermal Pad | power_in | Exposed thermal pad on the ESOP-8 package. Electrically connected to GND (pin 7). Must be soldered to the PCB ground plane for proper thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SCT2452STER
CAD (KiCad official)
- Symbol:
SCT2452STER - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (22 pp, sha256
a97363c67f20b5f7, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).