component
SCT2430STER
Public Unreviewedby Ray
SCT DC-DC Converters, ESOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSCT2430STER
SCT · DC-DC Converters · ESOP-8
SCT2430STER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap supply for the high-side MOSFET gate driver. Connect a 0.1uF ceramic capacitor from BOOT to SW; the bootstrap cap charges through an internal regulator when the low-side MOSFET is on or SW is low. BOOT-SW absolute max is 6V. |
| 2 | VIN | power_in | Input supply, 3.8V to 40V operating range (absolute max 42V). Connect a local high-frequency bypass capacitor from VIN to GND with the shortest possible path. |
| 3 | EN | input | Enable input with internal ~1.5uA pull-up current source and precision 1.18V rising / 1.1V falling threshold. Pull below 1.1V to disable the converter; float or tie to VIN to enable. A resistor divider from VIN to GND on EN programs the input UVLO threshold. High-voltage tolerant (abs max 42V). |
| 4 | RT/CLK | bidirectional | Dual-function timing pin. In resistor mode, a resistor from RT/CLK to GND programs the switching frequency (100kHz-2.2MHz; RT[kΩ] = 100000/fsw[kHz]). Alternatively, drive with an external clock (100kHz-2.2MHz, VIH ≥ 2V, VIL ≤ 0.4V, pulse width > 80ns) to synchronize via the internal PLL. Must not be left floating or shorted to ground. |
| 5 | FB | input | Feedback input to the inverting terminal of the internal trans-conductance error amplifier. Connect to the tap of an external resistor divider from VOUT to GND; the device regulates FB to the internal 0.8V ±1% reference (VOUT range 0.8V-40V). |
| 6 | COMP | output | Error amplifier output and loop compensation node. Connect the frequency-loop compensation network (typ. series R+C to GND) here. Also senses PSM entry (low clamp ~0.4V, high clamp ~3V). |
| 7 | GND | power_in | Device ground reference and power return. |
| 8 | SW | output | Switching node - source of the high-side MOSFET and drain of the low-side MOSFET. Connect to the external power inductor. Absolute max -0.3V to 42V. |
| 9 | Thermal Pad | power_in | Exposed die-attach pad on the package bottom. Electrically connected internally to GND (pin 7) and provides the primary heat-dissipation path. Must be soldered to the PCB ground plane for correct operation and thermal performance (RθJA = 42 °C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SCT2430STER
CAD (KiCad official)
- Symbol:
SCT2430STER - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (23 pp, sha256
94ab70b839a113fe, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).