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Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

markdown

SA571TS16ARDQ

GR · Special Purpose Amplifiers · TSSOP-16

SA571TS16ARDQ from GR, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CAP1.rect	passive	Channel 1 rectifier filter-capacitor terminal (CRECT1). External capacitor to ground sets the rectifier averaging time constant (τ = 10 kΩ × CRECT). Node is biased at VREF (1.8 V).
2	IN1.rect	input	Channel 1 rectifier input. Signal current from VIN flows through external 2.2 µF coupling cap and internal 10 kΩ (R1) into the full-wave rectifier summing node biased at VREF.
3	IN1.ΔG	input	Channel 1 variable-gain (ΔG) cell input. Signal current flows through external coupling cap and internal 20 kΩ (R2) into the ΔG summing node biased at VREF.
4	GND	power_in	Device ground return. Common ground for both channels and internal bandgap reference.
5	IN1.inv	input	Channel 1 op-amp inverting input, also tied internally to the ΔG cell output and to internal R3 (20 kΩ) / R4 (30 kΩ). Non-inverting input is internally tied to VREF (1.8 V).
6	R31.res	passive	Channel 1 summing-node/feedback tap, brought out from the internal R3 (20 kΩ) that goes from the summing node to the op-amp output. Allows compressor/expandor gain to be set by internal or external resistors.
7	OUT1	output	Channel 1 op-amp output. ±20 mA output current capability; capable of +13 dBm (3.5 VRMS) into 300 Ω.
8	THD1.trim	passive	Channel 1 THD (total-harmonic-distortion) trim terminal for the ΔG cell. Allows nulling of internal offset voltage to minimize even-harmonic distortion; node sits at VREF potential.
9	THD2.trim	passive	Channel 2 THD trim terminal for the ΔG cell. Allows nulling of internal offset voltage; node sits at VREF potential.
10	OUT2	output	Channel 2 op-amp output. ±20 mA output current capability; +13 dBm into 300 Ω.
11	R32.res	passive	Channel 2 summing-node/feedback tap through the internal R3 (20 kΩ) from summing node to op-amp output; enables external gain adjustment.
12	IN2.inv	input	Channel 2 op-amp inverting input, tied internally to the ΔG cell output and internal R3/R4 network; non-inverting input is internally tied to VREF.
13	VCC	power_in	Positive supply rail. Operating range 6 V to 18 V; typical ICC = 4.2 mA (4.8 mA max) with no signal.
14	IN2.ΔG	input	Channel 2 variable-gain (ΔG) cell input through internal 20 kΩ (R2) into the ΔG summing node biased at VREF.
15	IN2.rect	input	Channel 2 rectifier input through internal 10 kΩ (R1) into the full-wave rectifier summing node biased at VREF.
16	CAP2.rect	passive	Channel 2 rectifier filter-capacitor terminal (CRECT2). External cap to ground sets rectifier averaging time constant (τ = 10 kΩ × CRECT). Node biased at VREF.

Key specifications

Parameter	Value
Manufacturer	GR
Package	TSSOP-16
Category	Amplifiers/Comparators
Pins	16

Ordering variants

Same part, different packaging or reel option.

SA571TS16ARDQ

CAD (KiCad official)

Symbol: SA571TS16ARDQ
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GR datasheet (16 pp, sha256 a76b6868f174fe0d, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF