RT7272BGSP from Richtek Tech, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SW	output	Switch Node. Internal high-side/low-side N-MOSFET common drain node. Connect to the external L-C output filter. Absolute maximum -0.3V to (VIN + 0.3V).
2	BOOT	power_in	Bootstrap Supply for the High-Side Gate Driver. Connect a 100nF or greater ceramic capacitor from BOOT to SW. VBOOT - VSW absolute maximum is -0.3V to 6V.
3	EN	input	Enable Control Input. Logic-high (VIH ≥ 2V) enables the converter; logic-low (VIL ≤ 0.4V) forces the device into shutdown mode (IQ ≈ 0.5µA). Do not float.
4	GND	power_in	Ground. Signal and power ground return. Connect together with the exposed pad (pin 9) to a large PCB copper area for maximum thermal dissipation.
5	FB	input	Feedback Input. Connect to the converter output through a resistive divider to program the output voltage. Internal reference VREF = 0.8V (typ).
6	COMP	output	Compensation Node. Error amplifier output used to compensate the control loop. Connect a series R-C network from COMP to GND; an additional shunt capacitor to GND may be required in some designs.
7	RLIM	input	Current Limit Setting. Connect a resistor from RLIM to GND to program the high-side MOSFET peak current limit (adjustable from 1.9A to 7A per RLIM equation in Note 5).
8	VIN	power_in	Power Input. Supplies the internal regulator and the high-side MOSFET drain. Operating range 4.5V to 36V (absolute max 40V). Bypass with a suitable large ceramic capacitor placed close to the pin.
9	GND (Exposed Pad)	power_in	Exposed thermal pad. Must be soldered to a large PCB copper area connected to GND for maximum thermal dissipation. Electrically connected to pin 4 (GND).

Key specifications

Parameter	Value
Manufacturer	Richtek Tech
Package	SOIC-8-EP
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

RT7272BGSP

CAD (KiCad official)

Symbol: RT7272BGSP
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
3D model: SOIC-8-EP (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`rt7272bgsp.step`	193 KB	You want the bare part, or you mark your own boards.
`rt7272bgsp-etched.step`	1.8 MB	You want the part with `RT7272BGSP` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 453 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Richtek Tech datasheet (15 pp, sha256 cdf11346d1fc1345, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF