R5F100BEANA#40 from RENESAS, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P122/X2/EXCLK	bidirectional	Port 1.22 general-purpose I/O; also main-system crystal oscillator X2 and external clock input (EXCLK). Selected by clock-source configuration (CMC register).
2	VSS	power_in	Ground reference for the digital core and I/O. Also tie the exposed die pad to VSS.
3	P40/TOOL0	bidirectional	Port 4.0 general-purpose I/O; doubles as TOOL0 single-wire on-chip debug / flash-programming interface.
4	P137/INTP0	input	Port 13.7 input-only pin; also external interrupt request INTP0.
5	P121/X1	bidirectional	Port 1.21 general-purpose I/O; also main-system crystal oscillator X1 input.
6	REGC	passive	Internal voltage-regulator stabilization capacitor pin. Connect a 0.47 to 1 uF capacitor between REGC and VSS.
7	VDD	power_in	Main power supply, 1.6 to 5.5 V single-supply operation.
8	RESET	input	Active-low system reset input. Internal POR/LVD hold reset until VDD is valid.
9	P60/SCLA0	bidirectional	Port 6.0 N-ch open-drain I/O (6 V withstand); also IICA0 serial clock SCLA0. Requires external pull-up when used as I2C.
10	P61/SDAA0	bidirectional	Port 6.1 N-ch open-drain I/O (6 V withstand); also IICA0 serial data SDAA0. Requires external pull-up when used as I2C.
11	P62	bidirectional	Port 6.2 general-purpose I/O (N-ch open-drain capable). No alternate peripheral function on the 32-pin variant.
12	P31/TI03/TO03/INTP4/PCLBUZ0	bidirectional	Port 3.1 general-purpose I/O muxed with timer-array ch3 input/output (TI03/TO03), external interrupt INTP4, and programmable clock/buzzer output PCLBUZ0.
13	P70	bidirectional	Port 7.0 general-purpose I/O; no alternate peripheral function assigned in the 32-pin variant.
14	P30/INTP3/SCK11/SCL11	bidirectional	Port 3.0 general-purpose I/O muxed with external interrupt INTP3 and serial-array unit CSI11 clock (SCK11) or IIC11 clock (SCL11).
15	P50/INTP1/SI11/SDA11	bidirectional	Port 5.0 general-purpose I/O muxed with external interrupt INTP1 and CSI11 data-in (SI11) or IIC11 data (SDA11).
16	P51/INTP2/SO11	bidirectional	Port 5.1 general-purpose I/O muxed with external interrupt INTP2 and CSI11 data-out (SO11).
17	P17/TI02/TO02/(TxD0)	bidirectional	Port 1.7 general-purpose I/O muxed with timer-array ch2 (TI02/TO02); UART0 TxD0 can be redirected to this pin via PIOR.
18	P16/TI01/TO01/INTP5/(RxD0)	bidirectional	Port 1.6 general-purpose I/O muxed with timer-array ch1 (TI01/TO01) and external interrupt INTP5; UART0 RxD0 can be redirected here via PIOR.
19	P10/SCK00/SCL00/(TI07)/(TO07)	bidirectional	Port 1.0 general-purpose I/O muxed with CSI00 clock (SCK00) / IIC00 clock (SCL00). Timer-array ch7 (TI07/TO07) can be redirected here via PIOR.
20	P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)	bidirectional	Port 1.3 general-purpose I/O muxed with UART2 TxD2 and CSI20 data-out (SO20). IICA0 SDAA0 and timer-array ch4 (TI04/TO04) can be redirected here via PIOR.
21	P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)	bidirectional	Port 1.2 general-purpose I/O muxed with CSI00 data-out (SO00), UART0 TxD0 and on-chip debug external tool TOOLTxD. Timer-array ch5 (TI05/TO05) selectable via PIOR.
22	P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)	bidirectional	Port 1.5 general-purpose I/O muxed with programmable clock/buzzer output PCLBUZ1 and CSI20 clock (SCK20) / IIC20 clock (SCL20). Timer-array ch2 (TI02/TO02) selectable via PIOR.
23	P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)	bidirectional	Port 1.4 general-purpose I/O muxed with UART2 RxD2 and CSI20 data-in (SI20) / IIC20 data (SDA20). IICA0 SCLA0 and timer-array ch3 (TI03/TO03) selectable via PIOR.
24	P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)	bidirectional	Port 1.1 general-purpose I/O muxed with CSI00 data-in (SI00), UART0 RxD0, on-chip debug TOOLRxD, and IIC00 data (SDA00). Timer-array ch6 (TI06/TO06) selectable via PIOR.
25	P147/ANI18	bidirectional	Port 14.7 general-purpose I/O; also A/D converter analog input channel ANI18.
26	P23/ANI3	bidirectional	Port 2.3 general-purpose I/O; also A/D converter analog input channel ANI3.
27	P22/ANI2	bidirectional	Port 2.2 general-purpose I/O; also A/D converter analog input channel ANI2.
28	P21/ANI1/AVREFM	bidirectional	Port 2.1 general-purpose I/O; also ADC channel ANI1 and ADC negative-side reference input AVREFM.
29	P20/ANI0/AVREFP	bidirectional	Port 2.0 general-purpose I/O; also ADC channel ANI0 and ADC positive-side reference input AVREFP.
30	P01/ANI16/TO00/RxD1	bidirectional	Port 0.1 general-purpose I/O muxed with ADC channel ANI16, timer-array ch0 output TO00, and UART1 receive data RxD1.
31	P00/ANI17/TI00/TxD1	bidirectional	Port 0.0 general-purpose I/O muxed with ADC channel ANI17, timer-array ch0 input TI00, and UART1 transmit data TxD1.
32	P120/ANI19	bidirectional	Port 12.0 general-purpose I/O; also ADC analog input channel ANI19.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	QFN-32-EP(5x5)
Category	MCU
Pins	32

Ordering variants

Same part, different packaging or reel option.

R5F100BEANA#U0
R5F100BEANA#W0
R5F100BEANA#00
R5F100BEANA#20
R5F100BEANA#40

CAD (KiCad official)

Symbol: R5F100BEANA#40
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (207 pp, sha256 cce68189b7a22e8a, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF