PT4121EE23F
Public Unreviewedby Ray
PowTech CR PowTech Shanghai LED Drivers, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownPT4121EE23F
PowTech CR PowTech Shanghai · LED Drivers · SOT-23-6
PT4121EE23F from PowTech CR PowTech Shanghai, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply pin, 6 V to 60 V. Connect a decoupling capacitor from VIN to GND. Also serves as the reference node for the high-side current-sense comparator (VIN - VCSN). |
| 2 | CSN | input | LED current-sense input. Connect an external current-sense resistor R_CS between VIN and CSN to program average LED current; the internal comparator regulates (VIN-VCSN) to a nominal 200 mV threshold (194-206 mV) with ±15% hysteresis. |
| 3 | DIM | input | Logic-level dimming / enable input. Drive DIM low (<0.3 V) to turn off the current regulator, high (>2.5 V) to enable full LED current. Accepts either a PWM signal (100 Hz-20 kHz) or a DC voltage (0.5-2.5 V) to set output current. Internal 200 kΩ pull-up to a 4.2 V internal supply. |
| 4 | GND | power_in | Signal and power ground. Connect directly to the ground plane. |
| 5 | DRV | output | Gate-driver output for the external N-channel power MOSFET. Push-pull output (~6 Ω source / 2 Ω sink) swinging to VCC (~5 V); V_OH ≈ 4.8 V and V_OL ≤ 0.5 V at I_DRV = 10 mA. |
| 6 | VCC | power_out | Internal LDO regulator output, typically 5.0 V (4.5-5.5 V). Supplies internal circuitry and the gate driver. Connect a 1 µF decoupling capacitor from VCC to GND. Do not load externally. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | PowTech CR PowTech Shanghai |
| Package | SOT-23-6 |
| Category | LED-drv |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
PT4121EE23FPT4121EE23FESOH
CAD (KiCad official)
- Symbol:
PT4121EE23F - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
pt4121ee23f.step |
97 KB | You want the bare part, or you mark your own boards. |
pt4121ee23f-etched.step |
1.8 MB | You want the part with PT4121EE23F already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 461 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: PowTech CR PowTech Shanghai datasheet (11 pp, sha256
a09c8346fbe85b76, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).