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PMV42ENER

Public Unreviewed

by Ray

Nexperia MOSFETs, SOT-23. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componenttransistors-thyristorspmv42ener
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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PMV42ENER

Nexperia · MOSFETs · SOT-23

PMV42ENER from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate. Insulated control terminal of the N-channel MOSFET. V_GS(th) = 1.0 V min / 1.4 V typ / 2.0 V max (logic-level). Absolute maximum V_GS = ±20 V.
2 S passive Source. Current-return terminal of the N-channel MOSFET, typically tied to the load-return / ground rail in a low-side switch configuration. Also serves as the anode of the intrinsic body diode (V_SD ≈ 0.8 V typ at I_S = 1 A).
3 D passive Drain. High-side power terminal of the N-channel MOSFET. V_DS max = 30 V, continuous I_D up to 4.4 A (T_amb = 25 °C), peak I_DM = 18 A. R_DS(on) typ 29 mΩ at V_GS = 10 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • PMV42ENER

CAD (KiCad official)

  • Symbol: PMV42ENER
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 29cc4b3136a8da15, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF