PL5500 from POWLICON, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VADJ	input	Programs the voltage reference on VREF using a 0-2 V analog voltage or PWM signal. Tying VADJ to VDD forces VREF to a constant 2 V.
2	IADJ	input	Programs the current-limit reference on IREF using a 0-2 V analog voltage or PWM signal. Tying IADJ to VDD forces IREF to 2 V.
3	VSET	bidirectional	In charge mode (OTG low): a resistor from VSET to GND selects battery cell full-charge voltage (4.2/4.35/4.4/4.5 V). In discharge mode (OTG > 1.2 V): VSET outputs a voltage proportional to V(CSP2)-V(CSN2) for host monitoring of discharge current.
4	IREF	passive	Reference-voltage node for the input and output current-limit loops. Typically bypassed with a small capacitor to GND.
5	VREF	passive	Reference-voltage node for the voltage-control loop (2 V in discharge, 1.8 V in charge when VADJ = VDD). Typically bypassed to GND.
6	BRCOM	output	Battery internal-resistance compensation output. Voltage on this pin is proportional to V(CSP1)-V(CSN1) so the host can monitor charging current.
7	MODE	input	CCM/DCM mode select. Float (weak internal pull-up) selects DCM at light load; tie to GND to force CCM.
8	STAT	output	Status output. Reports charging status when OTG = Low, and functions as a PGOOD (power-good) indicator when OTG = High.
9	FREQ	input	Sets switching frequency: tie to GND for 150 kHz, tie to VDD for 300 kHz, or use a resistor divider between VDD/GND for 600 kHz (0.4-0.85 V) or 1200 kHz (0.85-1.8 V).
10	COMP	passive	Error-amplifier output / loop-compensation node. External RC network to GND sets loop dynamics.
11	VREG	input	Programs VBUS regulation voltage via a resistor divider. During heavy charging, when VBUS falls near the VREG setpoint the VREG loop takes over and reduces charging current. Not active in discharge mode.
12	FB2	input	VBUS voltage feedback in discharge mode. A resistor divider from VBUS to GND sets the regulated VBUS voltage (VFB2 regulation = 2 V).
13	CSN2	input	Negative input of the output (VBUS-side) current-sense amplifier. Max V(CSP2)-V(CSN2) is 0.6 V.
14	CSP2	input	Positive input of the output (VBUS-side) current-sense amplifier. Max V(CSP2)-V(CSN2) is 0.6 V.
15	VBUS	power_in	VBUS power rail (3.6-32 V operating, 40 V abs max). Sense/supply for the output-side of the buck-boost stage.
16	HG2	output	High-side gate drive 2 (VBUS-side high-side MOSFET). Integrated 2 A driver, referenced to SW2, powered from BST2.
17	BST2	passive	Bootstrap capacitor node for HG2. Connect capacitor from BST2 to SW2; abs max BST2-to-SW2 = 7 V.
18	SW2	passive	Switching node 2 (VBUS-side inductor terminal / bootstrap return). Abs max -0.3 V to 40 V.
19	LG2	output	Low-side gate drive 2 (VBUS-side low-side MOSFET). Integrated 2 A driver referenced to GND, powered from VCC.
20	VCC	power_in	5.0 V supply for the high-side and low-side gate drivers. Bypass to GND with a low-ESR capacitor.
21	LG1	output	Low-side gate drive 1 (VBAT-side low-side MOSFET). Integrated 2 A driver referenced to GND, powered from VCC.
22	SW1	passive	Switching node 1 (VBAT-side inductor terminal / bootstrap return). Abs max -0.3 V to 40 V.
23	BST1	passive	Bootstrap capacitor node for HG1. Connect capacitor from BST1 to SW1; abs max BST1-to-SW1 = 7 V.
24	HG1	output	High-side gate drive 1 (VBAT-side high-side MOSFET). Integrated 2 A driver, referenced to SW1, powered from BST1.
25	VBAT	power_in	Battery/input power rail (3.6-32 V operating, 40 V abs max). Also acts as output rail during OTG discharge operation.
26	CSP1	input	Positive input of the input/battery-side current-sense amplifier. Max V(CSP1)-V(CSN1) is 0.6 V.
27	CSN1	input	Negative input of the input/battery-side current-sense amplifier. Max V(CSP1)-V(CSN1) is 0.6 V.
28	EN	input	Enable input. Logic high enables the converter; logic low disables the entire PL5500. Weak internal pull-up; threshold ≈1.2 V with 200 mV hysteresis.
29	CELLS	input	Battery cell-count programming input. Resistor divider between VDD and GND sets 1-6 cells per V(CELLS) bins (0-0.9V=1, 4.5-5.5V=2, 0.9-1.8V=3, 1.8-2.7V=4, 2.7-3.6V=5, 3.6-4.5V=6).
30	OTG	input	Direction/mode select. Tie to GND for battery charging mode; drive above 1.2 V (e.g. to MODE) for battery discharging (OTG) mode. Hysteresis 200 mV.
31	TS	input	Battery temperature-sense input (NTC thermistor divider). Used for JEITA-style thermal qualification of charging.
32	VDD	power_in	5.4 V internal LDO output that powers the PL5500 control core. Bypass to GND with a low-ESR capacitor.

Key specifications

Parameter	Value
Manufacturer	POWLICON
Package	QFN-32-EP(4x4)
Category	Power Supply Chip
Pins	32

Ordering variants

Same part, different packaging or reel option.

PL5500IQN32A

CAD (KiCad official)

Symbol: PL5500
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: POWLICON datasheet (19 pp, sha256 351bf4738852f535, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF