The classic 40-pin PIC, an 8-bit Microchip microcontroller that taught a generation of engineers embedded C and assembly. It has 14 KB of flash program memory, 368 bytes of RAM, and 256 bytes of EEPROM, running the PIC16 RISC core at up to 20 MHz. The 40-pin DIP brings out 33 I/O across five ports (A-E), an 8-channel 10-bit ADC, three timers with CCP/PWM, and hardware USART, SPI, and I2C (MSSP), plus a parallel slave port. A crystal on OSC1/OSC2 or the internal options set the clock, and in-circuit programming uses PGC/PGD (RB6/RB7). Datasheet-verified 40-pin pinout.

Pinout

Pin	Name	Type	Function
1	MCLR/VPP	input	Master Clear (active-low reset) input and programming voltage input. Schmitt Trigger buffer. Tie through 10 kΩ pull-up to VDD in normal operation; VPP (~12-13 V) is applied during high-voltage ICSP programming.
2	RA0/AN0	bidirectional	PORTA bit 0 digital I/O with TTL input buffer; alternate function is analog input channel AN0 to the 10-bit ADC.
3	RA1/AN1	bidirectional	PORTA bit 1 digital I/O with TTL input buffer; alternate function is analog input channel AN1 to the 10-bit ADC.
4	RA2/AN2/VREF-/CVREF	bidirectional	PORTA bit 2 digital I/O (TTL); can be analog input AN2, ADC low reference input VREF-, or comparator voltage-reference output CVREF.
5	RA3/AN3/VREF+	bidirectional	PORTA bit 3 digital I/O (TTL); can be analog input AN3 or ADC high reference input VREF+.
6	RA4/T0CKI/C1OUT	bidirectional	PORTA bit 4 digital I/O with Schmitt Trigger input buffer, open-drain output stage; also the Timer0 external clock input T0CKI or Comparator 1 output C1OUT.
7	RA5/AN4/SS/C2OUT	bidirectional	PORTA bit 5 digital I/O (TTL); can be analog input AN4, SPI slave-select input SS, or Comparator 2 output C2OUT.
8	RE0/RD/AN5	bidirectional	PORTE bit 0 digital I/O (ST); can be the Parallel Slave Port read-strobe input RD (active-low) or analog input AN5.
9	RE1/WR/AN6	bidirectional	PORTE bit 1 digital I/O (ST); can be the Parallel Slave Port write-strobe input WR (active-low) or analog input AN6.
10	RE2/CS/AN7	bidirectional	PORTE bit 2 digital I/O (ST); can be the Parallel Slave Port chip-select input CS (active-low) or analog input AN7.
11	VDD	power_in	Positive supply for logic and I/O pins. Operating range 2.0 V to 5.5 V. Decouple with a 100 nF ceramic capacitor to VSS placed close to the pin (a 40-pin PDIP has two VDD pins; both must be tied to the same rail).
12	VSS	power_in	Ground reference for logic and I/O pins. Connect to the board ground plane; a 40-pin PDIP has two VSS pins that must be tied to the common ground.
13	OSC1/CLKI	input	Oscillator crystal input or external clock source input. Schmitt Trigger buffer in RC oscillator mode, CMOS input otherwise. Connect a crystal (with load caps) between OSC1 and OSC2, or drive with an external clock.
14	OSC2/CLKO	output	Oscillator crystal output; connects to crystal or resonator in Crystal Oscillator mode. In RC mode outputs CLKO at 1/4 of OSC1 frequency, indicating instruction-cycle rate.
15	RC0/T1OSO/T1CKI	bidirectional	PORTC bit 0 digital I/O (ST); can be Timer1 low-power oscillator output T1OSO or Timer1 external clock input T1CKI.
16	RC1/T1OSI/CCP2	bidirectional	PORTC bit 1 digital I/O (ST); can be Timer1 oscillator input T1OSI or CCP2 Capture2 input / Compare2 output / PWM2 output.
17	RC2/CCP1	bidirectional	PORTC bit 2 digital I/O (ST); can be CCP1 Capture1 input, Compare1 output, or PWM1 output (up to 10-bit PWM).
18	RC3/SCK/SCL	bidirectional	PORTC bit 3 digital I/O (ST); MSSP synchronous serial clock I/O - SCK for SPI mode or SCL for I2C mode.
19	RD0/PSP0	bidirectional	PORTD bit 0 digital I/O (ST); Parallel Slave Port data bit 0 when PSP is enabled.
20	RD1/PSP1	bidirectional	PORTD bit 1 digital I/O (ST); Parallel Slave Port data bit 1 when PSP is enabled.
21	RD2/PSP2	bidirectional	PORTD bit 2 digital I/O (ST); Parallel Slave Port data bit 2 when PSP is enabled.
22	RD3/PSP3	bidirectional	PORTD bit 3 digital I/O (ST); Parallel Slave Port data bit 3 when PSP is enabled.
23	RC4/SDI/SDA	bidirectional	PORTC bit 4 digital I/O (ST); MSSP SPI data input SDI or I2C data I/O SDA.
24	RC5/SDO	bidirectional	PORTC bit 5 digital I/O (ST); MSSP SPI data output SDO.
25	RC6/TX/CK	bidirectional	PORTC bit 6 digital I/O (ST); USART asynchronous transmit TX or USART synchronous clock CK.
26	RC7/RX/DT	bidirectional	PORTC bit 7 digital I/O (ST); USART asynchronous receive RX or USART synchronous data DT.
27	RD4/PSP4	bidirectional	PORTD bit 4 digital I/O (ST); Parallel Slave Port data bit 4 when PSP is enabled.
28	RD5/PSP5	bidirectional	PORTD bit 5 digital I/O (ST); Parallel Slave Port data bit 5 when PSP is enabled.
29	RD6/PSP6	bidirectional	PORTD bit 6 digital I/O (ST); Parallel Slave Port data bit 6 when PSP is enabled.
30	RD7/PSP7	bidirectional	PORTD bit 7 digital I/O (ST); Parallel Slave Port data bit 7 when PSP is enabled.
31	VSS	power_in	Ground reference for logic and I/O pins. Second VSS pin on 40-pin PDIP; must be tied to common ground with pin 12.
32	VDD	power_in	Positive supply for logic and I/O pins (2.0-5.5 V). Second VDD pin on 40-pin PDIP; must be tied to common VDD with pin 11 and decoupled with a 100 nF ceramic near the pin.
33	RB0/INT	bidirectional	PORTB bit 0 digital I/O with software-programmable weak pull-up; alternate function is the external interrupt input INT (Schmitt Trigger when configured as INT).
34	RB1	bidirectional	PORTB bit 1 digital I/O (TTL) with software-programmable weak pull-up. Part of the PORTB interrupt-on-change group (RB4-RB7 only).
35	RB2	bidirectional	PORTB bit 2 digital I/O (TTL) with software-programmable weak pull-up.
36	RB3/PGM	bidirectional	PORTB bit 3 digital I/O (TTL); alternate function is the low-voltage (single-supply) ICSP programming enable input PGM.
37	RB4	bidirectional	PORTB bit 4 digital I/O (TTL) with software-programmable weak pull-up and interrupt-on-change capability.
38	RB5	bidirectional	PORTB bit 5 digital I/O (TTL) with software-programmable weak pull-up and interrupt-on-change capability.
39	RB6/PGC	bidirectional	PORTB bit 6 digital I/O (TTL) with interrupt-on-change; alternate function is the in-circuit debugger and ICSP programming clock PGC (Schmitt Trigger when in Serial Programming mode).
40	RB7/PGD	bidirectional	PORTB bit 7 digital I/O (TTL) with interrupt-on-change; alternate function is the in-circuit debugger and ICSP programming data PGD (Schmitt Trigger when in Serial Programming mode).

Key specifications

Parameter	Value
Core	8-bit PIC (RISC, 35 instructions)
Flash	14 KB (8K x 14)
RAM	368 bytes
EEPROM	256 bytes
Max clock	20 MHz
I/O	33 (ports A-E)
ADC	8-channel 10-bit
Serial	USART + SPI + I2C (MSSP)
Supply voltage	2.0-5.5 V
Package	PDIP-40

Ordering variants

Same part, different packaging or reel option.

PIC16F877A-I/P (PDIP-40)
PIC16F877A-I/PT (TQFP-44)

CAD (KiCad official)

Symbol: MCU_Microchip_PIC16:PIC16F877A-IP
Footprint: Package_DIP:DIP-40_W15.24mm
3D model: DIP-40 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Technology datasheet (14 pp, sha256 3ab8d00885e545e3, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF