PI6CB33202ZDIEX from Diodes Incorporated, in a TQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	Internally connected for feedback loop. Do not connect this pin.
2	NC	unconnected	Internally connected for feedback loop. Do not connect this pin.
3	VDD_R	power_in	Power supply for input differential buffers. Nominal 3.3V (3.135V-3.465V).
4	IN+	input	Differential true clock input (HCSL). Accepts 100MHz reference by default, also 50/125/133.33MHz. Common-mode 150-900mV, swing 300-2900mV.
5	IN-	input	Differential complementary clock input (HCSL). Pair with IN+.
6	GND_DIG	power_in	Ground for digital circuitry.
7	SDATA	bidirectional	SMBus data line, 3.3V tolerant, CMOS. Used with SCLK for SMBus configuration of frequency, bandwidth, and OE control.
8	VDD_DIG	power_in	Power supply for digital circuitry, nominal 3.3V (3.135V-3.465V).
9	SCLK	input	SMBus clock input, 3.3V tolerant CMOS. Max SMBus frequency 500kHz.
10	VDDO	power_in	Power supply for differential outputs, nominal 3.3V.
11	NC	unconnected	Do not connect this pin.
12	NC	unconnected	Do not connect this pin.
13	Q0+	output	Differential true clock output (HCSL) for output pair 0. Default output impedance 85Ω.
14	Q0-	output	Differential complementary clock output (HCSL) for output pair 0.
15	OE0#	input	Active-low CMOS input for enabling Q0 pair. Internal pulldown (~120kΩ). 1 = disable outputs, 0 = enable outputs.
16	VDDA	power_in	Power supply for analog circuitry (PLL). Nominal 3.3V (3.135V-3.465V).
17	Q1+	output	Differential true clock output (HCSL) for output pair 1. Default output impedance 85Ω.
18	Q1-	output	Differential complementary clock output (HCSL) for output pair 1.
19	OE1#	input	Active-low CMOS input for enabling Q1 pair. Internal pulldown (~120kΩ). 1 = disable outputs, 0 = enable outputs.
20	NC	unconnected	Do not connect this pin.
21	VDDO	power_in	Power supply for differential outputs, nominal 3.3V. Second VDDO pin (tie to pin 10).
22	PD#	input	Active-low Power Down CMOS input with internal pullup (~120kΩ). Low enters Power Down Mode; subsequent high assertion latches strapping inputs and exits Power Down Mode.
23	SADR_TRI	input	Tri-level strapping input to select SMBus device address (0/M/1 → 1101011/1101100/1101101). Internal pulldown (~120kΩ).
24	BW_SEL_TRI	input	Tri-level strapping input to select PLL bandwidth mode: 0 = low-bandwidth PLL, M = PLL bypass, 1 = high-bandwidth PLL. Has both internal pullup and pulldown.
25	EPAD	power_in	Exposed thermal pad on package underside. Connect to ground.

Key specifications

Parameter	Value
Manufacturer	Diodes Incorporated
Package	TQFN-24-EP(4x4)
Category	RTC
Pins	25

Ordering variants

Same part, different packaging or reel option.

PI6CB33202ZDIEX

CAD (KiCad official)

Symbol: PI6CB33202ZDIEX
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: TQFN-24-EP(4x4) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`pi6cb33202zdiex.step`	277 KB	You want the bare part, or you mark your own boards.
`pi6cb33202zdiex-etched.step`	3.1 MB	You want the part with `PI6CB33202ZDIEX` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 772 faces against 158 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Diodes Incorporated datasheet (20 pp, sha256 43ca0c6f19ee260d, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF