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Contents

README

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PDTC123JT

Nexperia · Digital Transistors · SOT-23

PDTC123JT from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input pin. Connected through the built-in series bias resistor R1 = 2.2 kΩ (typ) to the base of the internal NPN transistor, with R2 = 47 kΩ from base to emitter/GND. Input voltage range -5 V to +12 V.
2 GND power_in Ground pin, connected to the emitter of the internal NPN transistor and to the low side of the internal base-emitter resistor R2.
3 O output Output pin (open collector of the internal NPN). Sinks up to 100 mA when the transistor is ON; withstands up to 50 V VCEO when OFF.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • PDTC123JT

CAD (KiCad official)

  • Symbol: PDTC123JT
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 5b3932371738ba33, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF