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Contents

README

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PDTC114ET

Nexperia · Digital Transistors · SOT-23

PDTC114ET from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I input Input (base) pin. Drives the built-in 10 kΩ series base resistor R1 into the NPN transistor's base. Typical on-state input voltage 1.8 V (min 2.5 V guaranteed), off-state input voltage 1.1 V; positive input voltage limit 40 V, negative -10 V.
2 GND passive Ground (emitter) pin. Connects to the emitter of the internal NPN transistor and the low side of R2 (10 kΩ base-emitter pull-down resistor).
3 O output Output (collector) pin. Open-collector output of the internal NPN transistor. Rated VCEO = 50 V, output current IO up to 100 mA, VCE(sat) ≤ 100 mV at IC = 10 mA, IB = 0.5 mA.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-23
Category Transistors/Thyristors
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • PDTC114ET

CAD (KiCad official)

  • Symbol: PDTC114ET
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 79eeed8f3c941b15, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF