A stereo audio DAC with an I2S input, in TSSOP-20, the chip on countless hi-fi DAC boards (including Raspberry Pi audio HATs). It converts a digital I2S stream (BCK, DIN, LRCK) into left/right analog line outputs at up to 32-bit, 384 kHz, with a ground-centered output made possible by an on-chip negative-rail charge pump, so no output coupling capacitors are needed. An internal PLL derives the system clock from the bit clock, meaning it works without a separate master clock (MCLK). Format, de-emphasis, filter, and soft-mute are set by pins for a jumperless design. Runs 3.3 V.

Pinout

Pin	Name	Type	Function
1	CPVDD	power_in	Charge pump power supply, 3.3 V nominal (3.1-3.46 V). Referenced to CPGND.
2	CAPP	output	Charge pump flying capacitor terminal for the positive rail. Connect the flying capacitor between CAPP and CAPM.
3	CPGND	power_in	Charge pump ground return.
4	CAPM	output	Charge pump flying capacitor terminal for the negative rail. Connect the flying capacitor between CAPP and CAPM.
5	VNEG	power_out	Negative charge pump rail terminal, nominally -3.3 V. Decouple to CPGND with the recommended reservoir capacitor.
6	OUTL	output	Analog audio output, DAC left channel. Ground-centered, 2.1 V_RMS full-scale; direct line drive down to 1 kΩ load, no DC blocking capacitor required.
7	OUTR	output	Analog audio output, DAC right channel. Ground-centered, 2.1 V_RMS full-scale; direct line drive down to 1 kΩ load, no DC blocking capacitor required.
8	AVDD	power_in	Analog power supply, 3.3 V nominal (3.0-3.46 V VCOM mode; 3.2-3.46 V VREF mode). Referenced to AGND.
9	AGND	power_in	Analog ground return. All grounds must be tied together within 0.2 V.
10	DEMP	input	De-emphasis control for 44.1 kHz sampling rate. Off (Low) / On (High). Failsafe LVCMOS Schmitt-trigger input.
11	FLT	input	Digital filter select: Normal latency (Low) / Low latency (High). Failsafe LVCMOS Schmitt-trigger input.
12	SCK	input	System (master) clock input. Up to 50 MHz; tie low to enable the internal PLL and generate SCK from BCK. Failsafe LVCMOS Schmitt-trigger input.
13	BCK	input	I2S/left-justified audio data bit clock input. Failsafe LVCMOS Schmitt-trigger input.
14	DIN	input	Audio serial data input (16-, 24-, or 32-bit PCM). Failsafe LVCMOS Schmitt-trigger input.
15	LRCK	input	Audio data word clock (left/right frame sync) input. Failsafe LVCMOS Schmitt-trigger input.
16	FMT	input	Audio format select: I2S (Low) / Left-justified (High). Failsafe LVCMOS Schmitt-trigger input.
17	XSMT	input	Soft mute control: Soft mute (Low) / Soft un-mute (High). Failsafe LVCMOS Schmitt-trigger input.
18	LDOO	power_out	Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal when DVDD is driven at 1.8 V.
19	DGND	power_in	Digital ground return.
20	DVDD	power_in	Digital power supply, 1.8 V (1.65-1.95 V) or 3.3 V (3.0-3.6 V). Referenced to DGND.

Key specifications

Parameter	Value
Type	Stereo audio DAC (I2S)
Resolution	up to 32-bit
Sample rate	up to 384 kHz
Output	ground-centered L/R (charge-pump negative rail)
Clocking	internal PLL, no MCLK required
SNR	112 dB
Control	pin-configured (FMT, FLT, DEMP, XSMT)
Package	TSSOP-20

Ordering variants

Same part, different packaging or reel option.

PCM5102APWR (TSSOP-20)
PCM5102APW (TSSOP-20, tube)

CAD (KiCad official)

Symbol: PCM5102A (generated from datasheet; KiCad has no symbol)
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (44 pp, sha256 a522083606b8e994, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF