Loads on click. Unloads only if this page sits in the background.
Contents

README

markdown

OC5228

OCX · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8

OC5228 from OCX, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LD input Analog / segmented dimming control input. Floating = full brightness (high mode); tied to VDD = 1/2 current low-brightness mode; 0.2V-1.2V analog input sets output current (linear analog dimming); below 0.2V shuts output off. Can also accept PWM with high level > 1.2V. Internal 20uA pull-down (ILD_F) supports segmented dimming.
2 PWM input PWM dimming input. High level enables output, low disables it; supports ultra-small duty ratios with a minimum response pulse width of 60ns. Rising threshold VPWM_H = 1.4V typ, falling VDIM_L = 0.8V typ. Pin floats to logic-high (output enabled) by default.
3 VDD power_in Chip supply pin. Powered via an external bleeder resistor R3 from VIN; internally clamped by a 5.5V shunt (VDDCLAMP typ 5.5V, IDDCLAMP max 10mA). Startup occurs when VDD reaches ~4.1V. Requires >=1.0uF bypass capacitor placed close to the pin. Operating current IDD ~2.5mA at VDD = 5.5V; quiescent IVDDQ ~1.2mA.
4 CS input Current-sense input. Connects to the source-side sense resistor Rcs; output current is regulated to Iout = 0.2V / Rcs. Constant-current reference VREF = 200mV typ (192-208mV); over-current threshold VCS = 216-264mV. Leading-edge blanking TLEB = 120ns typ. Absolute max VCS = -0.3 to 7.0V.
5 D output Drain of the internal 100V / 2A power MOSFET (switching node). RDS(on) = 200 mOhm typ at VGS = 5.5V; VDS rating 100V. Pins 5 and 6 are tied together internally and both must be connected to the inductor / freewheel-diode switch node.
6 D output Drain of the internal 100V / 2A power MOSFET (switching node), tied to pin 5. Connect both D pins together to the inductor / catch-diode node to share switch current.
7 GND power_in Device ground / power return. Pins 7 and 8 are both GND and should be tied together to the system ground plane close to the CS sense resistor to minimize sense-loop noise.
8 GND power_in Device ground / power return, tied to pin 7. Provides the return for internal control and MOS driver. Both GND pins must be connected on the board.

Key specifications

Parameter Value
Manufacturer OCX
Package SOP-8
Category PMIC
Pins 8

CAD (KiCad official)

  • Symbol: OC5228
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: OCX datasheet (None pp, sha256 1fb6ab4263618d59, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF