component

NE556DRG

Public Unreviewed

by Ray

HANSCHIP semiconductor Timers / Clock Oscillators, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentrtcne556drg
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF
Contents

README

markdown

NE556DRG

HANSCHIP semiconductor · Timers / Clock Oscillators · SOP-14

NE556DRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIS1 output Discharge pin for timer 1. Open-collector output that discharges the external timing capacitor when the internal flip-flop is set.
2 THR1 input Threshold input for timer 1. When voltage exceeds 2/3 VCC, the internal flip-flop resets and the output goes low.
3 CV1 input Control voltage input for timer 1. Allows external modulation of the internal 2/3 VCC threshold reference; typically bypassed to GND with a 10 nF capacitor.
4 RESET1 input Active-low reset for timer 1. Driving this pin below ~0.7 V forces the output low regardless of timing state; tie to VCC when not used.
5 OUT1 output Output of timer 1. Push-pull output capable of sourcing/sinking up to 200 mA, swinging between GND and near VCC.
6 TRIG1 input Trigger input for timer 1. A negative-going pulse below 1/3 VCC starts the timing cycle and drives the output high.
7 GND power_in Ground reference for both timers. Connect to system 0 V.
8 TRIG2 input Trigger input for timer 2. A negative-going pulse below 1/3 VCC starts the timing cycle and drives the output high.
9 OUT2 output Output of timer 2. Push-pull output capable of sourcing/sinking up to 200 mA, swinging between GND and near VCC.
10 RESET2 input Active-low reset for timer 2. Driving this pin below ~0.7 V forces the output low regardless of timing state; tie to VCC when not used.
11 CV2 input Control voltage input for timer 2. Allows external modulation of the internal 2/3 VCC threshold reference; typically bypassed to GND with a 10 nF capacitor.
12 THR2 input Threshold input for timer 2. When voltage exceeds 2/3 VCC, the internal flip-flop resets and the output goes low.
13 DIS2 output Discharge pin for timer 2. Open-collector output that discharges the external timing capacitor when the internal flip-flop is set.
14 VCC power_in Positive supply voltage for both timers. Operating range typically 4.5 V to 16 V. Bypass with a 100 nF ceramic capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-14
Category RTC
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • NE556DRG
  • NE556DRGD
  • NE556DRGN
  • NE556DRGP
  • NE556DRGPW

CAD (KiCad official)

  • Symbol: NE556DRG
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (5 pp, sha256 970a3f304f364539, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF