component
NCV5701ADR2G
Public Unreviewedby Ray
onsemi Isolators - Gate Drivers, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCV5701ADR2G
onsemi · Isolators - Gate Drivers · SOIC-8
NCV5701ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | input | Input signal to control the output. In galvanically isolated designs VIN is driven by an opto-coupler, pulse-transformer secondary, or digital-isolator output. VIN is internally clamped to 5.5 V and pulled up to VREF via a 1 MΩ resistor so the output stays low with no input. Signal is inverted from VIN to VO. Minimum pulse-width at VIN is required before VO is activated. |
| 2 | VREF | power_out | 5 V reference output (4.85-5.15 V, up to 20 mA) generated within the driver. Brought out for external bypassing (~100 nF recommended) and for powering low-bias circuits such as digital isolators. |
| 3 | FLT | output | Active-low FAULT output that signals the main controller that a fault (DESAT, UVLO, or TSD) has been encountered and the output deactivated. Capable of driving opto-couplers or digital isolators (sink 20 mA / source 25 mA max). |
| 4 | DESAT | input | Desaturation-detection input for IGBT fault sensing. A capacitor to GND on this pin sets a programmable blanking delay every ON cycle before the DESAT fault is processed, preventing false triggering. Threshold V_DESAT-THR ≈ 6.35 V; blanking charge current ≈ 0.24 mA. |
| 5 | VCC | power_in | Positive bias supply for the driver. Operating range is from UVLO (~13.5 V startup) up to 20 V (absolute max 22 V). A good-quality bypass capacitor to GND is required and must be placed close to the pin. |
| 6 | VO | output | IGBT gate driver output. Sources +4 A / sinks -6 A peak into the IGBT gate (typ. 6.8 A sink, 7.8 A source at Rg = 0.1 Ω, VCC = 15 V, VEE = -8 V). VO is actively pulled low during start-up and under fault conditions. |
| 7 | GND | power_in | Device ground. Should connect to the IGBT emitter with a short trace. All power-pin bypass capacitors should be referenced to this pin and kept close to it. |
| 8 | CLAMP | bidirectional | Active Miller Clamp pin. Provides clamping for the IGBT gate during the off period to protect it from parasitic (Miller) turn-on. Clamp activates at V_MC-THR ≈ 2.0 V above GND and can sink 500 mA. Tie directly to the IGBT gate with minimum trace length for best results. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
NCV5701ADR2GNCV5701BDR2GNCV5701CDR2G
CAD (KiCad official)
- Symbol:
NCV5701ADR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (22 pp, sha256
967fe6e8f755fee7, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).