component
NCP3170ADR2G
Public Unreviewedby Ray
onsemi DC-DC Converters, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP3170ADR2G
onsemi · DC-DC Converters · SOIC-8
NCP3170ADR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground pin - high-current return path for the low-side switch. Should be soldered to a large copper area to reduce thermal resistance and must be electrically connected to AGND (pin 3). |
| 2 | VIN | power_in | Main input supply, 4.5 V to 18 V. Powers internal control circuitry (monitored by voltage comparators), the internal power PMOS switch, and the internal linear regulator output. Must be decoupled close to the pin (e.g. 22 µF) due to high di/dt edges. |
| 3 | AGND | power_in | Analog / small-signal ground. All small-signal ground paths connect to AGND, which must tie to PGND at a single point to keep high-current returns out of the analog reference. |
| 4 | FB | input | Inverting input of the OTA error amplifier (VFB typ 0.8 V). Combined with the external compensation network on COMP, sets and regulates the output voltage via a resistor divider from VOUT. |
| 5 | COMP | output | Loop compensation node - output of the transconductance error amplifier (GM ≈ 201 µS). Connect an R-C network from COMP to AGND to compensate the current-mode control loop; place components as close to the pin as possible. |
| 6 | EN | input | Enable input (threshold ≈ 1.41 V, abs max VIN + 0.3 V). Pull high to enable the converter, low to disable it. Must not be left floating. |
| 7 | PG | output | Power-Good open-drain output (500 µA pull-down, abs max VIN + 0.3 V). Asserts when the output is inside the power-good window (~728 mV low / ~867 mV high thresholds on FB). If unused, may be tied to VSW for thermal relief - but not when the application turns on into a pre-bias. |
| 8 | VSW | power_out | Switch node - common drain of the internal high-side PMOS and low-side NMOS FETs (RDS(on) ≈ 90 mΩ HS / 25 mΩ LS at VIN = 12 V). Connect to the external inductor. At switch-off the inductor drives this pin below ground through the NMOS body diode with high dv/dt. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
NCP3170ADR2GNCP3170ADR2GBDR2G
CAD (KiCad official)
- Symbol:
NCP3170ADR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (26 pp, sha256
2f9cf78938a6bd7d, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).