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Contents

README

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NCP1623CDR2G

onsemi · AC-DC Controllers And Regulators · SOIC-8

NCP1623CDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Feedback pin connected to the inverting input of the transconductance error amplifier (VREF = 2.5 V typical) to monitor the scaled PFC output voltage. Also detects output transients to enable DRE, SOVP and FOVP. A ~250 nA sink current (IFB(UVP), 450 nA max) pulls the pin down to trigger UVP if the pin is accidentally left open.
2 VCC power_in IC bias supply. VCC(ON) ~10.5 V typ (11.25 V max), VCC(OFF) ~9.0 V typ, VCC absolute maximum 30 V. IC operating current ~2 mA (switching); sleep mode current in DIS ~100 uA.
3 DRV output Totem-pole gate driver output for the boost power MOSFET. Source/sink capability of -0.5 A / +0.8 A; internal clamp limits DRV high level to VDRV(HIGH) ~12 V typ (14 V max) when VCC is high. ROH ~10 ohm, ROL ~7 ohm; rise/fall times ~30/20 ns into 1 nF.
4 GND power_in Power supply and signal ground reference for the IC. All internal references and thresholds are measured with respect to this pin.
5 DIS input Disable/sleep-mode input. A high level or open circuit (internal ~530 kOhm pull-up, RDIS) disables the controller and reduces ICC to ICC(DIS) ~100 uA for low standby power. Sleep enter threshold VDIS(EN) ~1.8 V typ (rising); exit threshold VDIS(EX) ~1.1 V typ (falling). Absolute max rating -0.3 V to 9 V.
6 CS/ZCD input Multi-functional pin sensing MOSFET current (via RSENSE) and drain/auxiliary voltage. Provides OCP (VCS(OCP) ~500 mV), OVS (VCS(OVS) ~750 mV), ZCD (VZCD(TH-H/L) ~+/-40 mV), line-range/brown-out detection, short-to-ground detection, and OVP2 (VZCD(OVP2-EN) ~3.77 V, C-version only). Absolute max -0.3 V to 11.5 V with 5 mA clamp; VCS/ZCD(CL) ~9.5 V at 5 mA.
7 NC unconnected No Connect. True no-connect internally; PCB traces are allowed to pass under this pin.
8 VCTRL output Transconductance error-amplifier output; external type-2 compensation network to GND sets the regulation loop bandwidth (typically <20 Hz). Clamped between VCTRL(MIN) ~0.5 V and VCTRL(MAX) ~4.5 V. VCTRL controls on-time, VSFF dead-time, skip threshold (VCTRL(SKIP) ~0.56/0.62 V) and STATICOVP; grounded during OFF mode to provide soft-start at next restart.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • NCP1623CDR2G
  • NCP1623CDR2GSNT1G

CAD (KiCad official)

  • Symbol: NCP1623CDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 ab805ac6e3abe359, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF