component
NCP1593AMNTWG
Public Unreviewedby Ray
onsemi DC-DC Converters, DFN-10-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCP1593AMNTWG
onsemi · DC-DC Converters · DFN-10-EP(3x3)
NCP1593AMNTWG from onsemi, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect on the NCP1593A. May be left floating or tied to GND. (On NCP1593B this pin is an additional LX.) |
| 2 | LX | power_out | Switching node - drain of the internal high-side PMOS and low-side NMOS. Connect the output inductor to this pin (tie pins 2 and 3 together). |
| 3 | LX | power_out | Switching node - drain of the internal high-side PMOS and low-side NMOS. Connect the output inductor to this pin (tie pins 2 and 3 together). |
| 4 | PG | output | Power Good - open-drain output from the Power-Good comparator. High-impedance when FB voltage is within regulation (rising threshold 0.54 V typ, falling 0.51 V typ); otherwise pulled low (VRPG ≈ 130 mV at 2.5 mA). |
| 5 | EN | input | Enable input. Logic high (>1.4 V) turns the part on; logic low (<0.4 V) shuts it off. An internal ~1.4 µA pull-up forces the part into the enabled state when the pin is left floating. |
| 6 | FB | input | Feedback input to the error amplifier. Connect a resistor divider from VOUT to this pin to program the regulated output; internal reference VFB ≈ 0.6 V. |
| 7 | SS | passive | Soft-start. An external capacitor to GND sets the soft-start ramp time (charged by ISS ≈ 0.7 µA). Leaving the pin open uses the default 500 µs internal soft-start. (On NCP1593B this pin is NC and must be left floating.) |
| 8 | VCCA | power_in | Analog/internal-bias supply input (called VCC in the pin table, VCCA in the pin-connection diagram and application circuit). Bypass with a 0.1 µF ceramic capacitor to GND and tie directly to VCCP on the board. Range 4.0 V to 5.5 V. |
| 9 | VCCP | power_in | Power-stage supply input for the internal high-side PMOS. Tie to VCCA and bypass with input capacitance. Range 4.0 V to 5.5 V. |
| 10 | VCCP | power_in | Power-stage supply input for the internal high-side PMOS. Tie to VCCA and bypass with input capacitance. Range 4.0 V to 5.5 V. |
| EP | GND | power_in | Exposed thermal pad - device ground and primary thermal path. Must be soldered to the PCB ground plane for proper electrical and thermal operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | DFN-10-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 11 |
Ordering variants
Same part, different packaging or reel option.
NCP1593AMNTWGNCP1593AMNTWGBMNTWG
CAD (KiCad official)
- Symbol:
NCP1593AMNTWG - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (14 pp, sha256
e51c579bf424fdbd, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).