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Contents

README

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NCN8026AMNTXG

onsemi · Interface - Specialized · QFN-24-EP(4x4)

NCN8026AMNTXG from onsemi, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSEL0 input Card VCC voltage-select bit 0. Combined with VSEL1 selects 5 V, 3 V or 1.8 V (5V/3V mode when VSEL0=Low; 1.8V/3V mode when VSEL0=High; VSEL1 selects between the two levels of the chosen mode).
2 CS input Active-low chip select. When CS is Low the control and signal pins are configured normally; when CS is High, CMDVCC, VSEL0, VSEL1, CLKDIV1, CLKDIV2 and RSTIN are latched, and I/Ouc, AUX1uc, AUX2uc go to high-impedance pull-up.
3 VDDP power_in Regulator power supply (2.7-5.5 V depending on selected CVCC mode). When VDDP falls below ~2.5 V the card pins are disabled.
4 PRES input Active-low card-presence input (card present when PRES=Low) with an ~8 ms built-in debounce timer. Intended for normally-open (NO) smart-card connectors; may be left open when unused.
5 PRES input Active-high card-presence input (card present when PRES=High) with an ~8 ms built-in debounce timer. Intended for normally-closed (NC) smart-card connectors; may be left open when unused.
6 CI/O bidirectional Bidirectional level-shifted I/O to smart-card connector pin C7. Internal ~11 kΩ pull-up to CVCC provides high-impedance idle state for the card I/O line.
7 CAUX2 bidirectional Bidirectional level-shifted auxiliary AUX2 I/O to smart-card connector pin C8. Internal ~11 kΩ pull-up to CVCC provides high-impedance idle state.
8 CAUX1 bidirectional Bidirectional level-shifted auxiliary AUX1 I/O to smart-card connector pin C4. Internal ~11 kΩ pull-up to CVCC provides high-impedance idle state.
9 CCLK output Smart-card clock output (drives card pin C3). Derived from CLKIN through the internal clock divider and level shifter; supports up to 27 MHz.
10 CRST output Smart-card RESET output to card connector pin C2. Level-shifted from the host RSTIN signal to CVCC level.
11 CVCC power_out Programmable card power-supply output (card pin C1). Delivers 1.8 V / 3.0 V / 5.0 V (±5%) at up to 70 mA, programmable via VSEL0/VSEL1. Requires an external distributed ceramic capacitor 80 nF-1.2 µF (ESR < 100 mΩ) between CVCC and CGND.
12 PORADJ input Power-on-reset threshold adjustment input. External resistor divider on VDD sets the VDD UVLO / POR threshold (rising ~1.24 V, falling ~1.19 V typical at PORADJ). Tie to GND when unused.
13 CMDVCC input Active-low command-VCC / activation-enable input. Toggling CMDVCC High→Low with a card present starts the ISO7816 activation sequence; when CMDVCC=High the CVCC output is pulled low and the internal LDO is disabled (unless latched by CS).
14 RSTIN input Host-side reset input, referenced to VDD. Level-shifted internally and driven to the smart card via CRST at the CVCC-programmed voltage.
15 VDD power_in System-controller (host) power supply, 1.6-5.5 V. Sets the host-side logic-level of the level shifters. A 0.1 µF decoupling capacitor is required. When VDD falls below ~1.45 V the card pins are disabled.
16 GND power_in Digital / host-side ground reference.
17 INT output Active-low interrupt request to the host. Asserted on card-presence changes detected via PRES/PRES and on faults (e.g. CVCC overload). Open-drain-like output with an ~50 kΩ pull-up (available with metal-change option).
18 CLKIN input External clock input to the internal clock divider (up to 27 MHz). Divider ratio (1/1, 1/2, 1/4, 1/8) is selected by CLKDIV1/CLKDIV2 and produces CCLK to the card.
19 I/Ouc bidirectional Host-side bidirectional I/O corresponding to card CI/O. Level-translated between the microcontroller (VDD domain) and the smart card (CVCC domain). Built-in ~11 kΩ pull-up provides high-impedance state.
20 AUX1uc bidirectional Host-side bidirectional auxiliary line corresponding to card CAUX1 (C4). Level-translated between the microcontroller (VDD) and the card (CVCC); built-in ~11 kΩ pull-up.
21 AUX2uc bidirectional Host-side bidirectional auxiliary line corresponding to card CAUX2 (C8). Level-translated between the microcontroller (VDD) and the card (CVCC); built-in ~11 kΩ pull-up.
22 CLKDIV1 input Clock-divider select bit 1. Combined with CLKDIV2 programs CCLK = CLKIN divided by 1, 1/2, 1/4 or 1/8 (see clock-division table).
23 CLKDIV2 input Clock-divider select bit 2. Combined with CLKDIV1 programs the CLKIN→CCLK division ratio.
24 VSEL1 input Card VCC voltage-select bit 1. Combined with VSEL0 chooses CVCC = 5 V, 3 V or 1.8 V (VSEL1=High picks the higher level of the mode chosen by VSEL0).
25 GND power_in Exposed thermal pad - regulator (card-side) power-supply ground. Must be soldered to the PCB ground plane for proper electrical operation and thermal dissipation.

Key specifications

Parameter Value
Manufacturer onsemi
Package QFN-24-EP(4x4)
Category Communication Interface Chip/UART/485/232
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • NCN8026AMNTXG

CAD (KiCad official)

  • Symbol: NCN8026AMNTXG
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (15 pp, sha256 c3d6be7a248da33b, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF