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N32G455CCL7

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by Ray

Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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N32G455CCL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

N32G455CCL7 from Nations Technologies Inc, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery-backed supply for RTC, LSE oscillator, and backup registers. Connect to a 1.8-3.6 V cell when VDD is absent; otherwise tie to VDD.
2 PC13/TAMPER-RTC bidirectional GPIO PC13, alternate TAMPER-RTC. TC I/O powered from VBAT switch (max drive ~3 mA, 2 MHz / 30 pF load); not intended for high-drive loads.
3 PC14/OSC32_IN bidirectional LSE 32.768 kHz crystal input, or GPIO PC14 when LSE is not used. TC I/O powered from the VBAT switch.
4 PC15/OSC32_OUT bidirectional LSE 32.768 kHz crystal output, or GPIO PC15 when LSE is not used. TC I/O powered from the VBAT switch.
5 PD0/OSC_IN bidirectional HSE crystal input (4-32 MHz) by default after reset on LQFP48/64. Can be reconfigured by software as GPIO PD0.
6 PD1/OSC_OUT bidirectional HSE crystal output by default after reset on LQFP48/64. Can be reconfigured by software as GPIO PD1.
7 NRST bidirectional Bidirectional active-low reset. Drive low externally to reset the MCU; also driven low internally by watchdog/POR/BOR.
8 VSSA power_in Analog ground for ADC, DAC, OPAMP, COMP, VREF and analog switches. Connect to a clean analog ground plane.
9 VDDA power_in Analog supply for ADC, DAC, OPAMP, COMP and internal VREF. Operating range 1.8-3.6 V; must be tied to VDD when analog blocks are used.
10 PA0/WKUP bidirectional GPIO PA0. Alternates: WKUP wake-up input, USART2_CTS, ADC1_IN1, TIM2/5/8 CH1/ETR, COMP1_OUT/INM, SPI3_MISO. TTa I/O, 3.3 V-tolerant with analog function.
11 PA1 bidirectional GPIO PA1. Alternates: USART2_RTS, ADC1_IN2, TIM5_CH2, TIM2_CH2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP, SPI3_MOSI/I2S3_SD.
12 PA2 bidirectional GPIO PA2. Alternates: USART2_TX, TIM5_CH3, ADC12_IN3, TIM2_CH3, COMP2_OUT, OPAMP1_INM, OPAMP2_INM.
13 PA3 bidirectional GPIO PA3. Alternates: USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4, OPAMP1_INM, OPAMP1_VINP, COMP5_INP.
14 PA4 bidirectional GPIO PA4. Alternates: SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS, TSC_CHN0, and many COMPx_INM / OPAMPx_INM / I2C2_SCL redefined functions.
15 PA5 bidirectional GPIO PA5. Alternates: SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK, TSC_CHN1, and many COMPx_INM / OPAMPx_VINM/VINP / I2C2_SDA redefined functions.
16 PA6 bidirectional GPIO PA6. Alternates: SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, COMP1_OUT, QSPI_IO0, TIM1_BKIN, OPAMP1_VOUT, COMP2_OUT.
17 PA7 bidirectional GPIO PA7. Alternates: SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1, COMP2_OUT, TIM1_CH1N, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP, COMP6_INM.
18 PB0 bidirectional GPIO PB0. Alternates: ADC3_IN12, TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX, OPAMP2_VINP, COMP3_INP, COMP5_OUT.
19 PB1 bidirectional GPIO PB1. Alternates: ADC2_IN3, TIM3_CH4, TIM8_CH3N, COMP4_OUT, TIM1_CH3N, OPAMP2_VOUT, UART6_RX, COMP2_INM, COMP1_OUT.
20 PB2/BOOT1 bidirectional GPIO PB2, also BOOT1 boot-mode select strap. Alternates: ADC2_IN13, UART4_TX, SPI1_NSS. Sample-at-reset for boot mode.
21 PB10 bidirectional GPIO PB10. Fail-safe I/O. Alternates: I2C2_SCL, USART3_TX, TIM2_CH3, COMP5_INM, OPAMP3_VINM, OPAMP4_VINM, COMP1_INP, COMP3_OUT.
22 PB11 bidirectional GPIO PB11. Alternates: I2C2_SDA, USART3_RX, ADC3_IN1, TIM2_CH4, OPAMP4_VOUT, COMP2_INP, COMP5_OUT.
23 VSS_1 power_in Digital ground. Connect to system ground plane.
24 VDD_1 power_in Digital supply, 1.8-3.6 V. Decouple locally with 100 nF ceramic (see supply-decoupling recommendations in section 4).
25 PB12 bidirectional GPIO PB12. Alternates: SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ADC4_IN3, COMP3_INM, OPAMP4_VOUT, COMP4_OUT.
26 PB13 bidirectional GPIO PB13. Alternates: SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ADC3_IN5, UART5_TX, COMP4_INM.
27 PB14 bidirectional GPIO PB14. Alternates: SPI2_MISO, TIM1_CH2N, USART3_RTS, ADC4_IN4, TSC_CHN2, COMP3_INP, UART5_RX.
28 PB15 bidirectional GPIO PB15. Alternates: SPI2_MOSI, I2S2_SD, TIM1_CH3N, ADC4_IN5, TSC_CHN3, COMP4_INP.
29 PA8 bidirectional GPIO PA8, 5 V tolerant (FT). Alternates: USART1_CK, TIM1_CH1, MCO clock output.
30 PA9 bidirectional GPIO PA9, 5 V tolerant. Alternates: USART1_TX, TIM1_CH2, TSC_DOUT, I2C4_SCL.
31 PA10 bidirectional GPIO PA10, 5 V tolerant. Alternates: USART1_RX, TIM1_CH3, I2C4_SDA.
32 PA11/USBDM bidirectional USB 2.0 FS device D- line. Also GPIO PA11, 5 V tolerant. Alternates: USART1_CTS, CAN1_RX, TIM1_CH4, COMP1_OUT, COMP5_OUT.
33 PA12/USBDP bidirectional USB 2.0 FS device D+ line. Also GPIO PA12, 5 V tolerant. Alternates: USART1_RTS, CAN1_TX, TIM1_ETR, COMP2_OUT, COMP6_OUT.
34 PA13/JTMS-SWDIO bidirectional SWD data / JTAG TMS after reset. Also reconfigurable as GPIO PA13 or UART4_TX.
35 VSS_2 power_in Digital ground.
36 VDD_2 power_in Digital supply, 1.8-3.6 V. Decouple locally with 100 nF ceramic.
37 PA14/JTCK-SWCLK bidirectional SWD clock / JTAG TCK after reset. Also reconfigurable as GPIO PA14 or UART4_RX.
38 PA15/JTDI bidirectional JTAG data input (JTDI) after reset. Alternates when remapped: GPIO PA15, SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS, TIM8_CH1N.
39 PB3/JTDO bidirectional JTAG data output / TRACESWO after reset. Alternates: GPIO PB3, SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS, TIM8_BKIN.
40 PB4/NJTRST bidirectional JTAG reset (active low) after reset. Alternates: GPIO PB4, SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX, TIM8_ETR.
41 PB5 bidirectional GPIO PB5, 5 V tolerant. Alternates: I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX, TIM1_BKIN.
42 PB6 bidirectional GPIO PB6. Alternates: I2C1_SCL, TIM4_CH1, TSC_CHN20, USART1_TX, CAN2_TX, COMP5_OUT.
43 PB7 bidirectional GPIO PB7. Alternates: I2C1_SDA, TIM4_CH2, TSC_CHN21, USART1_RX, COMP6_OUT.
44 BOOT0 input Boot-mode strap sampled at reset. Combined with BOOT1 (PB2) it selects boot from Flash, System Memory (bootloader), or SRAM.
45 PB8 bidirectional GPIO PB8. Alternates: TIM4_CH3, SDIO_D4, COMP1_OUT, TSC_CHN22, I2C1_SCL, CAN1_RX, UART5_TX.
46 PB9 bidirectional GPIO PB9. Alternates: TIM4_CH4, SDIO_D5, COMP2_OUT, TSC_CHN23, I2C1_SDA, CAN1_TX, UART5_RX.
47 VSS_3 power_in Digital ground.
48 VDD_3 power_in Digital supply, 1.8-3.6 V. Decouple locally with 100 nF ceramic.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-48(7x7)
Category MCU
Pins 48

Ordering variants

Same part, different packaging or reel option.

  • N32G455CCL7CBL7
  • N32G455CCL7
  • N32G455CCL7CEQ7
  • N32G455CCL7RBL7
  • N32G455CCL7RCL7
  • N32G455CCL7REL7
  • N32G455CCL7MBL7
  • N32G455CCL7MCL7
  • N32G455CCL7MEL7
  • N32G455CCL7VBL7
  • N32G455CCL7VCL7
  • N32G455CCL7VEL7

CAD (KiCad official)

  • Symbol: N32G455CCL7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (87 pp, sha256 d7532f973fd1b7fb, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF