component

n32g452ccl7

Public Unreviewed

by Ray

Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentmcun32g452ccl7
Overview Files Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Contents

README

markdown

N32G452CCL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

N32G452CCL7 from Nations Technologies Inc, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Battery backup supply (1.8-3.6 V) for the RTC, LSE oscillator and backup registers when VDD is not present.
2 PC13/TAMPER-RTC bidirectional Backup-domain I/O; default function TAMPER-RTC (anti-tamper detection / RTC alarm output). PC13/14/15 are fed from a backup switch limited to 3 mA total; when driven as outputs, max 2 MHz and max load 30 pF.
3 PC14/OSC32_IN bidirectional Backup-domain I/O; default 32.768 kHz LSE crystal input (OSC32_IN). Same 3 mA / 2 MHz / 30 pF restriction as PC13.
4 PC15/OSC32_OUT bidirectional Backup-domain I/O; default 32.768 kHz LSE crystal output (OSC32_OUT). Same 3 mA / 2 MHz / 30 pF restriction as PC13.
5 OSC_IN/PD0 input HSE crystal input (OSC_IN) after reset - 4-32 MHz external crystal. Can be remapped as general-purpose PD0 in LQFP48 (input only when used as GPIO).
6 OSC_OUT/PD1 output HSE crystal output (OSC_OUT) after reset - 4-32 MHz external crystal. Can be remapped as general-purpose PD1 in LQFP48 (output only when used as GPIO).
7 NRST bidirectional Bidirectional active-low reset pin with internal weak pull-up. Driven low by internal reset sources; pulled low externally to force reset.
8 VSSA power_in Analog ground return for ADC, DAC, VREF and internal analog references. Tie to system ground.
9 VDDA power_in Analog supply for the ADC, DAC and internal reference (1.8-3.6 V). On LQFP48 the internal VREF+ is tied to VDDA (dedicated VREF+/VREF- pins are only broken out on LQFP100/128).
10 PA0-WKUP bidirectional General-purpose I/O (TTa, 3.3 V analog-capable). Default WKUP standby wake-up input. Alt: USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, SPI3_MISO, ADC1_IN1.
11 PA1 bidirectional General-purpose I/O (TTa). Alt: USART2_RTS, TIM5_CH2, TIM2_CH2, SPI3_MOSI, I2S3_SD, ADC1_IN2.
12 PA2 bidirectional General-purpose I/O (TTa). Alt: USART2_TX, TIM5_CH3, TIM2_CH3, ADC12_IN11.
13 PA3 bidirectional General-purpose I/O (TTa). Alt: USART2_RX, TIM5_CH4, TIM2_CH4, ADC1_IN4.
14 PA4 bidirectional General-purpose I/O (TTa). Alt: SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS, I2C2_SCL.
15 PA5 bidirectional General-purpose I/O (TTa). Alt: SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK, I2C2_SDA.
16 PA6 bidirectional General-purpose I/O (TTa). Alt: SPI1_MISO, TIM8_BKIN, TIM3_CH1, QSPI_IO0, TIM1_BKIN, ADC1_IN3.
17 PA7 bidirectional General-purpose I/O (TTa). Alt: SPI1_MOSI, TIM8_CH1N, TIM3_CH2, QSPI_IO1, TIM1_CH1N, ADC2_IN4.
18 PB0 bidirectional General-purpose I/O (TC 3.3 V). Alt: TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX.
19 PB1 bidirectional General-purpose I/O (TTa). Alt: TIM3_CH4, TIM8_CH3N, TIM1_CH3N, UART6_RX, ADC2_IN3.
20 PB2/BOOT1 bidirectional General-purpose I/O (TTa) also sampled at reset as BOOT1 to select boot mode together with BOOT0. Alt: UART4_TX, SPI1_NSS, ADC2_IN13.
21 PB10 bidirectional General-purpose I/O (TC). Alt: I2C2_SCL, USART3_TX, TIM2_CH3.
22 PB11 bidirectional General-purpose I/O (TC). Alt: I2C2_SDA, USART3_RX, TIM2_CH4.
23 VSS_1 power_in Digital ground for the core / I/O domain (pair with VDD_1).
24 VDD_1 power_in Digital supply (1.8-3.6 V) for the core / I/O domain - decouple with 100 nF next to the pin plus a bulk cap shared with the other VDD pins.
25 PB12 bidirectional General-purpose I/O (TC). Alt: SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX.
26 PB13 bidirectional General-purpose I/O (TC). Alt: SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, UART5_TX.
27 PB14 bidirectional General-purpose I/O (TC). Alt: SPI2_MISO, TIM1_CH2N, USART3_RTS, UART5_RX.
28 PB15 bidirectional General-purpose I/O (TC). Alt: SPI2_MOSI, I2S2_SD, TIM1_CH3N.
29 PA8 bidirectional General-purpose I/O (FT, 5 V-tolerant). Alt: USART1_CK, TIM1_CH1, MCO clock output.
30 PA9 bidirectional General-purpose I/O (FT). Alt: USART1_TX, TIM1_CH2, I2C4_SCL.
31 PA10 bidirectional General-purpose I/O (FT). Alt: USART1_RX, TIM1_CH3, I2C4_SDA.
32 PA11 bidirectional General-purpose I/O (FT) also serving as USB 2.0 FS D- (USBDM). Alt: USART1_CTS, CAN1_RX, TIM1_CH4.
33 PA12 bidirectional General-purpose I/O (FT) also serving as USB 2.0 FS D+ (USBDP). Alt: USART1_RTS, CAN1_TX, TIM1_ETR.
34 PA13/JTMS-SWDIO bidirectional Default JTMS / SWDIO debug pin after reset (SWJ-DP, weak pull-up). Alt: PA13 GPIO, UART4_TX.
35 VSS_2 power_in Digital ground for the core / I/O domain (pair with VDD_2).
36 VDD_2 power_in Digital supply (1.8-3.6 V) for the core / I/O domain - decouple with 100 nF next to the pin.
37 PA14/JTCK-SWCLK bidirectional Default JTCK / SWCLK debug clock after reset (SWJ-DP, weak pull-down). Alt: PA14 GPIO, UART4_RX.
38 PA15/JTDI bidirectional Default JTDI JTAG data-in after reset (weak pull-up). Alt: PA15 GPIO, SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS, TIM8_CH1N.
39 PB3/JTDO bidirectional Default JTDO JTAG data-out / TRACESWO after reset. Alt: PB3 GPIO, SPI3_SCK/I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS, TIM8_BKIN.
40 PB4/NJTRST bidirectional Default NJTRST JTAG reset (active-low, weak pull-up) after reset. Alt: PB4 GPIO, SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX, TIM8_ETR.
41 PB5 bidirectional General-purpose I/O (FT). Alt: I2C1_SMBA, SPI3_MOSI/I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX, TIM1_BKIN.
42 PB6 bidirectional General-purpose I/O (TC). Alt: I2C1_SCL, TIM4_CH1, USART1_TX, CAN2_TX.
43 PB7 bidirectional General-purpose I/O (TC). Alt: I2C1_SDA, TIM4_CH2, USART1_RX.
44 BOOT0 input Boot-mode select input sampled at reset. With BOOT1 (PB2) it chooses between main Flash, system-memory bootloader (UART/USB) and SRAM.
45 PB8 bidirectional General-purpose I/O (TC). Alt: TIM4_CH3, SDIO_DAT4, I2C1_SCL, CAN1_RX, UART5_TX.
46 PB9 bidirectional General-purpose I/O (TC). Alt: TIM4_CH4, SDIO_DAT5, I2C1_SDA, CAN1_TX, UART5_RX.
47 VSS_3 power_in Digital ground for the core / I/O domain (pair with VDD_3).
48 VDD_3 power_in Digital supply (1.8-3.6 V) for the core / I/O domain - decouple with 100 nF next to the pin.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-48(7x7)
Category MCU
Pins 48

Ordering variants

  • N32G452CCL7N32G452CBL7
  • N32G452CCL7
  • N32G452CCL7N32G452CEL7
  • N32G452CCL7N32G452RBL7
  • N32G452CCL7N32G452RCL7
  • N32G452CCL7N32G452REL7
  • N32G452CCL7N32G452MBL7
  • N32G452CCL7N32G452MCL7
  • N32G452CCL7N32G452MEL7
  • N32G452CCL7N32G452VBL7
  • N32G452CCL7N32G452VCL7
  • N32G452CCL7N32G452VEL7
  • N32G452CCL7N32G452QCL7
  • N32G452CCL7N32G452QEL7

CAD (KiCad official)

  • Symbol: N32G452CCL7
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (None pp, sha256 5f6acc8eefb11678, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

PCB Footprint

Open full view ↗
Loads on click. Unloads when scrolled away or the tab is hidden.

Datasheet

Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Download PDF